MIC2155 datasheet(13/33 Pages) MICREL

13 / 33 page

Micrel, Inc.

MIC2155/2156

May 2009

M9999-052709-A

(408) 944-0800

VEN1/2

VSS

OUT

Slope = ISS/CSS

Figure 3. Soft Start Waveforms

Figure 4. Soft Start Circuit

The output voltage starts to rise when VSS is

approximately 1 diode drop above ground, 0.6V.

The startup delay and output voltage risetime can be

approximated using the formula shown below.

OUT

Risetime

0.6V

Delay

The soft start pin is discharged under the following

conditions:

• EN1 pin de-asserted

• UVLO on the VIN1 or VDD pins

• Overcurrent

• Overvoltage (latched off)

Enable

There is an enable pin for each of the two channels.

Asserting EN1 will enable Channel 1 gate drive and

release the soft start circuit. De-asserting EN1 will

disable the gate drive, discharge CSS and disable VDD. It

will bring the controller into a low current off state.

Enable 2 only controls switching of Channel 2. Disabling

Channel 2 stops the switching of the power FETs on

Channel 2 which reduces the VDD current draw. This can

improve efficiency when operating at low output current,

especially when large MOSFETs are used.

Supply Voltages and Internal References

The MIC2155/6 is powered from a 4.5V to 14.5V supply.

The two input supply pins (VIN1 and VIN2) are

connected together in most applications. They are

powered separately in configurations with two input

supply voltages.

VIN1 supplies an internal LDO, which generates the

VDD supply voltage. VDD is used to power the gate drive

circuitry and must be externally decoupled to the power

ground pins (PGND1 and PGND2). A 10µF Ceramic

capacitor is recommended for most applications. The

AVDD pin is the supply pin for the Bandgap reference

and internal analog circuits. A small RC filter

(10ohm/0.1µF) connected to AVDD is recommended to

help attenuate switching noise from the VDD supply.

The dropout of the internal VDD regulator causes VDD

to drop if VIN1 is below 6V. When operating below 6V,

VDD may be jumpered to VIN1. This bypasses the

internal LDO and prevents VDD from dropping out.

An LDO or simple series pass regulator can be used to

limit the VDD voltage for applications with an input

voltage that spans above and below the 6V maximum

Vdd limit. Figures 5 and 6 illustrate two examples of

regulating VDD with external circuitry.

CIN

1µF

CVDD

10µF

CBST

Figure 5. LDO Regulator

MIC2155 Datasheet(PDF) 13 Page - Micrel Semiconductor

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