33937 datasheet(32/48 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33937

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

RESET AND ENABLE

The 33937 has three power modes of operation described

in Table 6. There are three global control inputs (RST, EN1,

EN2), which together with the status of the VDD and VLS,

control the behavior of the IC.

The operating status of the IC can be described by the

following three modes:

Sleep Mode

- When RST is low, the IC is in Sleep mode.

The current consumption of the IC is at minimum.

• Standby Mode - The RST input is high while one of the

Enable inputs is low. The IC is fully biased up and

operating, all the external FETs are actively turned off

by both High Side and Low Side gate drives. The IC is

ready to enter the Enable mode.

• Enable Mode - In order to enter the Enable mode

(normal mode of operation), and to operate the outputs,

the RST input must be high, and both Enable inputs

EN1 and EN2 must also be high.

• After entry to Enable Mode, the IC requires a pulse on

Px_LS in order to charge the bootstrap capacitor before

allowing the Px_HS to turn on. This pulse should be

long enough to guarantee the bootstrap capacitor is

charged (typically less than 50 µs), but the IC does not

enforce this condition. If there is an alternate means of

pre-charging the bootstrap capacitor, i.e. an external

resistor from Px_HS_S to GND, then a very brief pulse

of 100 ns is sufficient to reset the logic.

Table 6. Functions of RST, EN1 and EN2 Pins

RST

EN1, EN2

Mode of Operation (Driver Condition)

Sleep Mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. All error

and SPI registers are cleared. The internal 5.0 V regulator is turned off and VDD is pulled low. All logic outputs except

SO are clamped to VSS.

Standby Mode - IC fully biased up and all functions are operating, the output drivers actively turn off all of the external

FETs (after initialization). The SPI port is functional. Logic level outputs are driven with low impedance. SO is high

impedance unless CS is low. VDD, Charge Pump and VLS regulators are all operating. The IC is ready to move to Enable

Mode.

Enable Mode - (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs

require a pulse on Px_LS before corresponding HS outputs will turn on in order to charge the bootstrap capacitor. All

error pin and register bits are active if detected.

Table 7. Functional Ratings

(TJ = -40°C to 150°C and supply voltage range VSUP = VPWR = 5.0 to 45 V, C = 0.47 µF)

Characteristic

Value

Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open (55)

(Driver output is switched off, high-impedance mode)

Low (<1.0 V)

Default State of input pin Px_HS, CS if left open (55)

(Driver output is switched off, high-impedance mode)

High (>2.0 V)

Notes

55.

To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources.

33937 Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

33937 Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc

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