33937 datasheet(37/48 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33937

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

STATUS REGISTERS

After any SPI command, the status of the IC is reported in

the return value from the SPI port. There are four variants of

the NULL command used to read various status in the IC.

Other commands return a general status word in the Status

There are four Status Registers in the IC. Status

Registers one through three are used to read or confirm

internal IC settings.

Status Register 0 (Status Latch Bits)

This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command

returns the following data:

Table 15. Status Register 0

SPI Data Bits

765

432

Results

Read

RESET

Event

Write

Error

Framing

Error

Phase

Error

Over-current

Low

VLS

DESAT

Detected on

any Channel

TLIM

Detected on

any Channel

Reset

100

000

All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits

set. If the status is still present, that bit will not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1

respectively.

• Bit 0–is a flag for Over-temperature on any channel. This bit is the OR of the latched three internal TLIM detectors.This

flag can generate an interrupt if the appropriate mask bit is set.

• Bit 1–is a flag for Desaturation Detection on any channel. This bit is the OR of the latched three internal High Side

desaturation detectors and phase error logic. Faults are also detected on the Low Side as phase errors. A phase error is

generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR

of phase errors from each phase. Each phase error is the OR of the HS and LS phase errors. An HS phase error (which

will also trigger the desaturation detector) occurs when the HS FET is commanded on, and the Px_HS_S is still low in the

deadtime duration after it is driven ON. Similarly, a LS phase error occurs when the LS FET is commanded on, and the

Px_HS_S is still high in the deadtime duration after the FET is driven ON. This flag can generate an interrupt if the

appropriate mask bit is set.

• Bit 2– is a flag for Low Supply Voltage. This bit is latched, thus a prior low voltage event is returned once before being

cleared on read. This flag can generate an interrupt if the appropriate mask bit is set.

• Bit 3–is a flag for the output of the Over-current Comparator. This flag can generate an interrupt if the appropriate mask

bit is set.

• Bit 4–is a flag for a Phase Error. If any Phase comparator output is not at the expected value when just one of the

individual high or Low Side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output

with the output driver state, and blanked for the duration of the desaturation blanking interval. This flag can generate an

interrupt if the appropriate mask bit is set.

• Bit 5–is a flag for a Framing Error. A framing error is an SPI message not containing a multiple of eight bits (a 0-length

message is also a framing error on 33937A). SCLK toggling while measuring the Deadtime calibration pulse is also a

framing error. This would typically be a transient or permanent hardware error, perhaps due to noise on the SPI lines. This

flag can generate an interrupt if the appropriate mask bit is set.

• Bit 6–indicates a Write Error After the Lock bit is set. A write error is any attempted write to the MASKn, Mode, or a

Deadtime command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one

defined in the Table 8. This would typically be a software error. This flag can generate an interrupt if the appropriate mask

bit is set.

• Bit 7–is set upon exiting RST. It can be used to test the interrupt mechanism or to flag for a condition where the IC gets

reset without the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set.

33937 Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc

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