ST8012 datasheet(9/47 Pages) SITRONIX

9 / 47 page

ST8012

V1.6

9/47

2004/09/08

(Common mode)

SYMBOL

FUNCTION

VDD

Logic system power supply pin, connected to +2.5 to +5.5 V.

VSS

Ground pin, connected to 0 V.

V0, V1

V2, V3

This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined

by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through

changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must

maintain the relative magnitudes shown below.

V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss

When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages

shown below. The voltage settings are selected using the LCD bias set command.

1/120 Duty

1/112 Duty

1/96Duty

1/80Duty

1/64Duty

1/48 Duty

1/30 Duty

1/11*V0 ,1/9*V0

1/11*V0, 1/9*V0

1/10*V0, 1/8*V0

1/9*V0, 1/7*V0 1/9*V0, 1/7*V0 1/7*V0, 1/5*V0 1/6*V0, 1/5*V0

2/11*V0,1/9*V0

2/11*V0, 2/9*V0

2/10*V0, 2/8*V0

2/9*V0, 2/7*V0 2/9*V0, 2/7*V0 2/7*V0, 2/5*V0 2/6*V0, 2/5*V0

9/11*V0, 7/9*V0

8/10*V0, 6/8*V0

7/9*V0, 5/7*V0 7/9*V0, 5/7*V0 5/7*V0, 3/5*V0 4/6*V0, 3/5*V0

10/11*V0,8/9*V0

9/10*V0, 7/8*V0

8/9*V0, 6/7*V0 8/9*V0, 6/7*V0 6/7*V0, 4/5*V0 5/6*V0, 4/5*V0

Shift clock pulse input pin for bi-directional shift register

* Data is shifted at the falling edge of the clock pulse.

XRST

System Reset pin .When low level active.

If not used the hardware reset, this pin must pull height.

The XRST L PULSE timing min value is 200us and max value is 0.5s

L/R

Input pin for selecting the shift direction of bi-directional shift register

Data is shifted from COMSEG119 to COMSEG0 when set to VSS level "L", and data is shifted from

COMSEG0 to COMSEG119 when set to VDD level "H".

Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in

Functional Operations.

XDISPOFF

Control input pin for output of non-select level

The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the

LCD drive circuit.

When set to VSS level "L", the LCD drive output pins (COMSEG0-COMSEGx) are set to level Vss.

When set to "L”, the contents of the shift register are reset to not reading data. When the /DISPOFF

function is canceled, the driver outputs non-select level (V1 or V4), and the shift data is read at the

next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is

shown in AC characteristics, the shift data is not read correctly.

Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.

AC signal input pin for LCD drive waveform

The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the

LCD drive circuit.

ST8012 Datasheet(PDF) 9 Page - Sitronix Technology Co., Ltd.

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