LPC2364 datasheet(21/59 Pages) NXP

21 / 59 page

LPC2364_65_66_67_68_6

Product data sheet

Rev. 06 — 1 February 2010

21 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can

be programmed to generate an interrupt on a rising edge, a falling edge, or both. The

edge detection is asynchronous, so it may operate when clocks are not present such as

during Power-down mode. Each enabled interrupt can be used to wake up the chip from

Power-down mode.

7.8.1 Features

• Bit level set and clear registers allow a single instruction to set or clear any number of

bits in one port.

• Direction control of individual bits.

• All I/O default to inputs after reset.

• Backward compatibility with other earlier devices is maintained with legacy Port 0 and

Port 1 registers appearing at the original addresses on the APB.

7.9 Ethernet

The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC

designed to provide optimized performance through the use of DMA hardware

acceleration. Features include a generous suite of control registers, half or full duplex

operation, flow control, control frames, hardware acceleration for transmit retry, receive

packet filtering and wake-up on LAN activity. Automatic frame transmission and reception

with scatter-gather DMA off-loads many operations from the CPU.

The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access

the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic

in the LPC2364/65/66/67/68 takes place on a different AHB subsystem, effectively

separating Ethernet activity from the rest of the system. The Ethernet DMA can also

access the USB SRAM if it is not being used by the USB block.

The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII

(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial

bus.

7.9.1 Features

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.

– Flexible transmit and receive frame options.

– Virtual Local Area Network (VLAN) frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to shared SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory traffic optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

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