LPC2364 datasheet(16/59 Pages) NXP

16 / 59 page

LPC2364_65_66_67_68_6

Product data sheet

Rev. 06 — 1 February 2010

16 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

[8]

Pad provides special analog functionality.

[9]

When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

[10] Pad provides special analog functionality.

[11] Pad provides special analog functionality.

[12] Pad provides special analog functionality.

[13] Pad provides special analog functionality.

[14] Pad provides special analog functionality.

Functional description

7.1 Architectural overview

The LPC2364/65/66/67/68 microcontroller consists of an ARM7TDMI-S CPU with

emulation support, the ARM7 local bus for closely coupled, high-speed access to the

majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals,

and the AMBA APB for connection to other on-chip peripheral functions. The

microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte

order.

The LPC2364/65/66/67/68 implements two AHB in order to allow the Ethernet block to

operate without interference caused by other system activity. The primary AHB, referred

to as AHB1, includes the VIC and GPDMA controller.

The second AHB, referred to as AHB2, includes only the Ethernet block and an

associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary

AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into

off-chip memory or unused space in memory residing on AHB1.

In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function,

and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2

are the ARM7 and the Ethernet block.

AHB peripherals are allocated a 2 MB range of addresses at the very top of the 4 GB

ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the

AHB address space. Lower speed peripheral functions are connected to the APB. The

AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocated a

2 MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is

allocated a 16 kB address space within the APB address space.

The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers

high performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed complex

instruction set computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

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