LPC2364 datasheet(32/59 Pages) NXP

32 / 59 page

LPC2364_65_66_67_68_6

Product data sheet

Rev. 06 — 1 February 2010

32 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the

code execution and peripherals activities will resume after 4 cycles expire. If the main

external oscillator was used, the code execution will resume when 4096 cycles expire.

The customers need to reconfigure the PLL and clock dividers accordingly.

7.24.4.3

Power-down mode

Power-down mode does everything that Sleep mode does, but also turns off the IRC

oscillator and the flash memory. This saves more power, but requires waiting for

resumption of flash operation before execution of code or data access in the flash memory

can be accomplished.

On the wake-up of Power-down mode, if the IRC was used before entering Power-down

mode, it will take IRC 60

μs to start-up. After this 4 IRC cycles will expire before the code

execution can then be resumed if the code was running from SRAM. In the meantime, the

flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100

μs flash start-up

time. When it times out, access to the flash will be allowed. The customers need to

reconfigure the PLL and clock dividers accordingly.

7.24.4.4

Deep power-down mode

Deep power-down mode is similar to the Power-down mode, but now the on-chip

regulator that supplies power to the internal logic is also shut off. This produces the lowest

possible power consumption without removing power from the entire chip. Since the Deep

power-down mode shuts down the on-chip logic power supply, there is no register or

memory retention, and resumption of operation involves the same activities as a full chip

reset.

If power is supplied to the LPC2364/65/66/67/68 during Deep power-down mode,

wake-up can be caused by the RTC Alarm interrupt or by external Reset.

While in Deep power-down mode, external device power may be removed. In this case,

the LPC2364/65/66/67/68 will start up when external power is restored.

Essential data may be retained through Deep power-down mode (or through complete

powering off of the chip) by storing data in the Battery RAM, as long as the external power

to the VBAT pin is maintained.

7.24.4.5

Power domains

The LPC2364/65/66/67/68 provides two independent power domains that allow the bulk

of the device to have power removed while maintaining operation of the RTC and the

battery RAM.

On the LPC2364/65/66/67/68, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while

the VDD(DCDC)(3V3) pin powers the on-chip DC-to-DC converter which in turn provides

power to the CPU and most of the peripherals.

Depending on the LPC2364/65/66/67/68 application, a design can use two power options

to manage power consumption.

LPC2364 Datasheet(PDF) 32 Page - NXP Semiconductors

LPC2364 Datasheet(HTML) 32 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL