LPC2364 datasheet(33/59 Pages) NXP

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LPC2364_65_66_67_68_6

Product data sheet

Rev. 06 — 1 February 2010

33 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

The first option assumes that power consumption is not a concern and the design ties the

VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power

supply for both pads, the CPU, and peripherals. While this solution is simple, it does not

support powering down the I/O pad ring “on the fly” while keeping the CPU and

peripherals alive.

The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and

a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-to-DC

converter powered independently from the I/O pad ring enables shutting down of the I/O

pad power supply “on the fly”, while the CPU and peripherals stay active.

The VBAT pin supplies power only to the RTC and the battery RAM. These two functions

require a minimum of power to operate, which can be supplied by an external battery.

When the CPU and the rest of chip functions are stopped and power removed, the RTC

can supply an alarm output that may be used by external hardware to restore chip power

and resume operation.

7.25 System control

7.25.1 Reset

Reset has four sources on the LPC2364/65/66/67/68: the RESET pin, the Watchdog

reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a

Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating

voltage attains a usable level, starts the Wake-up timer (see description in Section 7.24.3

“Wake-up timer”), causing reset to remain asserted until the external Reset is

de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash

controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the Boot Block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.25.2 Brownout detection

The LPC2364/65/66/67/68 includes 2-stage monitoring of the voltage on the

VDD(DCDC)(3V3) pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal

to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt

Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor

the signal by reading a dedicated status register.

The second stage of low-voltage detection asserts Reset to inactivate the

LPC2364/65/66/67/68 when the voltage on the VDD(DCDC)(3V3) pins falls below 2.65 V. This

Reset prevents alteration of the flash as operation of the various elements of the chip

would otherwise become unreliable due to low voltage. The BOD circuit maintains this

reset down below 1 V, at which point the power-on reset circuitry maintains the overall

Reset.

Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this

hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event

loop to sense the condition.

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