LPC2364 datasheet(44/59 Pages) NXP

44 / 59 page

LPC2364_65_66_67_68_6

Product data sheet

Rev. 06 — 1 February 2010

44 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

10. Dynamic characteristics

[1]

Parameters are valid over operating temperature range unless otherwise specified.

[2]

Typical ratings are not guaranteed. The values listed are at room temperature (25

°C), nominal supply voltages.

[3]

LPC2364HBD only.

[4]

Bus capacitance Cb in pF, from 10 pF to 400 pF.

Table 7.

Dynamic characteristics

Tamb = −40 °C to +85 °C for standard devices, −40 °C to +125 °C for LPC2364HBD only, unless otherwise specified; VDD(3V3)

over specified ranges.[1]

Symbol

Parameter

Conditions

Min

Typ[2]

Max

Unit

ARM processor clock frequency

foper

operating frequency

CCLK;

−40 °C to +85 °C

MHz

CCLK; > 85

°C

[3] 1

MHz

IRC;

−40 °C to +85 °C

3.96

4.04

MHz

IRC; > 85

°C

[3] 3.98

4.02

4.06

MHz

External clock

fosc

oscillator frequency

MHz

Tcy(clk)

clock cycle time

1000

tCHCX

clock HIGH time

Tcy(clk) × 0.4

tCLCX

clock LOW time

Tcy(clk) × 0.4

tCLCH

clock rise time

tCHCL

clock fall time

I2C-bus pins (P0[27] and P0[28])

tf(o)

output fall time

VIH to VIL

20 + 0.1

× C

[4]

SSP interface

tsu(SPI_MISO)

SPI_MISO set-up time

Tamb = 25 °C; measured

in SPI Master mode; see

Figure 13

Table 8.

Dynamic characteristics of USB pins (full-speed) (LPC2364/66/68 only)

CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3), unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

rise time

10 % to 90 %

8.5

13.8

fall time

10 % to 90 %

7.7

13.7

tFRFM

differential rise and fall time

matching

tr / tf

109

VCRS

output signal crossover voltage

1.3

2.0

tFEOPT

source SE0 interval of EOP

see Figure 12

160

175

tFDEOP

source jitter for differential transition

to SE0 transition

see Figure 12

−2

tJR1

receiver jitter to next transition

−18.5

+18.5

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