LPC2364 datasheet(22/59 Pages) NXP

22 / 59 page

LPC2364_65_66_67_68_6

Product data sheet

Rev. 06 — 1 February 2010

22 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

– Receive filtering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching.

– Wake-on-LAN power management support allows system wake-up: using the

receive filters or a magic frame detection filter.

• Physical interface:

– Attachment of external PHY chip through standard RMII interface.

– PHY register access is available via the MIIM interface.

7.10 USB interface (LPC2364/66/68 only)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and a number (127 maximum) of peripherals. The host controller allocates the USB

bandwidth to attached devices through a token based protocol. The bus supports hot

plugging, unplugging, and dynamic configuration of the devices. All transactions are

initiated by the host controller.

7.10.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of register interface, serial interface engine, endpoint buffer memory, and the

DMA controller. The serial interface engine decodes the USB data stream and writes data

to the appropriate end point buffer memory. The status of a completed USB transfer or

error condition is indicated via status registers. An interrupt is also generated if enabled.

The DMA controller when enabled transfers data between the endpoint buffer and the

USB RAM.

7.10.2 Features

• Fully compliant with USB 2.0 specification (full speed).

• Supports 32 physical (16 logical) endpoints with a 4 kB USB endpoint buffer RAM.

• Supports Control, Bulk, Interrupt and Isochronous endpoints.

• Scalable realization of endpoints at run time.

• Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.

• Supports SoftConnect and GoodLink features.

• While USB is in the Suspend mode, LPC2364/65/66/67/68 can enter one of the

reduced power modes and wake up on a USB activity.

• Supports DMA transfers with the DMA RAM of 8 kB on all non-control endpoints.

• Allows dynamic switching between CPU-controlled and DMA modes.

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