LPC2364 datasheet(15/59 Pages) NXP

15 / 59 page

LPC2364_65_66_67_68_6

Product data sheet

Rev. 06 — 1 February 2010

15 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

[1]

5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.

[2]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input,

digital section of the pad is disabled.

[3]

5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,

digital section of the pad is disabled.

[4]

Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide

output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

Open-drain configuration applies to all functions on this pin.

[5]

Pad provides digital I/O and USB functions (LPC2364/66/68 only). It is designed in accordance with the USB specification, revision 2.0

(Full-speed and Low-speed mode only).

[6]

5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.

[7]

5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

TCK

5[1]

C1[1]

TCK — Test Clock for JTAG interface. This clock must be slower than 1

⁄

6 of

the CPU clock (CCLK) for the JTAG interface to operate

RTCK

100[1]

B2[1]

I/O

RTCK — JTAG interface control signal.

Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to

operate as trace port after reset.

RSTOUT

RSTOUT — This is a 3.3 V pin. LOW on this pin indicates

LPC2364/65/66/67/68 being in Reset state.

Note: This pin is available in LPC2364FBD100, LPC2365FBD100,

LPC2366FBD100, LPC2367FBD100, and LPC2368FBD100 devices only

(LQFP100 package).

RESET

17[7]

F3[7]

External reset input: A LOW on this pin resets the device, causing I/O

ports and peripherals to take on their default states, and processor

execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

22[8][9]

H2[8][9]

Input to the oscillator circuit and internal clock generator circuits.

XTAL2

23[8][9]

G3[8][9]

Output from the oscillator amplifier.

RTCX1

16[8]

F2[8]

Input to the RTC oscillator circuit.

RTCX2

18[8]

G1[8]

Output from the RTC oscillator circuit.

VSS

15, 31,

41, 55,

72, 97,

83[10]

B3, B7,

C9, F1,

G7, J6,

K3 [10]

ground: 0 V reference.

VSSA

11[11]

E1[11]

analog ground: 0 V reference. This should nominally be the same voltage

as VSS, but should be isolated to minimize noise and error.

VDD(3V3)

28, 54,

71,

96[12]

A3, C10,

H9,

K2[12]

3.3 V supply voltage: This is the power supply voltage for the I/O ports.

VDD(DCDC)(3V3)

13, 42,

84[13]

A7, E4,

H6[13]

3.3 V DC-to-DC converter supply voltage: This is the supply voltage for

the on-chip DC-to-DC converter only.

VDDA

10[14]

E2[14]

analog 3.3 V pad supply voltage: This should be nominally the same

voltage as VDD(3V3) but should be isolated to minimize noise and error. This

voltage is used to power the ADC and DAC.

VREF

12[14]

E3[14]

ADC reference: This should be nominally the same voltage as VDD(3V3) but

should be isolated to minimize noise and error. Level on this pin is used as

a reference for ADC and DAC.

VBAT

19[14]

G2[14]

RTC pin power supply: 3.3 V on this pin supplies the power to the RTC

peripheral.

Table 4.

Pin description …continued

Symbol

Ball

Type

Description

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