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LPC2364 Datasheet(PDF) 45 Page - NXP Semiconductors |
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LPC2364 Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 59 page ![]() LPC2364_65_66_67_68_6 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 1 February 2010 45 of 59 NXP Semiconductors LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers [1] Characterized but not implemented as production test. Guaranteed by design. [1] Number of program/erase cycles. [2] tret specified for < 1ppm. tJR2 receiver jitter for paired transitions 10 % to 90 % −9 - +9 ns tEOPR1 EOP width at receiver must reject as EOP; see Figure 12 [1] 40 - - ns tEOPR2 EOP width at receiver must accept as EOP; see Figure 12 [1] 82 - - ns Table 8. Dynamic characteristics of USB pins (full-speed) …continued (LPC2364/66/68 only) CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3), unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Table 9. Dynamic characteristics of flash Tamb = −40 °C to +85 °C for standard devices, −40 °C to +125 °C for LPC2364HBD only, unless otherwise specified; VDD(3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 - - cycles tret retention time powered; < 100 cycles [2] 10 - - years unpowered; < 100 cycles 20 - - years |
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