DM9161 datasheet(9/50 Pages) DAVICOM

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DM9161

10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver

Final

Version: DM9161-DS-F05

September 10, 2008

5.4 Mode, 2 pins

Pin No.

Pin Name

I/O

Description

PWRDWN

Power Down Control

Asserted high to force the DM9161 into power down mode. When in

power down mode, most of the DM9161 circuit block’s power is turned

off, only the MII management interface (MDC, MDIO) logic is available

(the PHY should respond to management transactions and should not

generate spurious signals on the MII)). To leave power down mode, the

DM9161 needs the hardware or software reset with the PWRDWN pin

low

CABLESTS

/LINKSTS

(D)

Cable Status or Link Status

This pin is used to indicate the status of the cable connection when

power up reset latch low (Default)

0 = Without cable connection

1 = With cable connection

This pin is used to indicate the status of the Link connection when power

up reset latch high

0 = Without link

1 = With link

5.5 Bias and Clock, 4 pins

Pin No.

Pin Name

I/O

Description

BGRESG

Bandgap Ground

BGRES

O Bandgap Voltage Reference Resistor 6.8K ohm

XT2

I/O Crystal Output; REF_CLK input for RMII mode

XT1

Crystal Input

5.6 Power, 13 pins

Pin No.

Pin Name

I/O

Description

1,2

AVDD

Analog Receive Power

AVDD

Analog Transmit Power

AGND

Analog Receive Ground

AGND

Analog Transmit Ground

AGND

Analog Substrate Ground

23,30,39,41

DVDD

Digital Power

15,33,44

DGND

Digital Ground

DM9161 Datasheet(PDF) 9 Page - Davicom Semiconductor, Inc.

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