SE97BTP datasheet(18/53 Pages) NXP

18 / 53 page

SE97B_1

Product data sheet

Rev. 01 — 27 January 2010

18 of 53

NXP Semiconductors

SE97B

DDR memory module temp sensor with integrated SPD

Up to eight memory devices can be connected on a single I2C-bus. Each one is given a

3-bit on the hardware selectable address (A2, A1, A0) inputs. The device only responds

when the 4-bit fixed and hardware selectable bits are matched. The 8th bit is the

read/write bit. This bit is set to 1 or 0 for read and write protection, respectively.

The corresponding device acknowledges during the ninth bit time when there is a match

on the 7-bit address.

The device does not acknowledge when there is no match on the 7-bit address or when

the device is already in permanent write protection mode and is programmed with any

write protection instructions (i.e., PWP, RWP, CWP).

7.10.2.1

Permanent Write Protection (PWP)

If the software write-protection has been set with the PWP instruction, the first 128 bytes

of the memory are permanently write-protected. This write-protection cannot be cleared

by any instruction, or by power-cycling the device. Also, once the PWP instruction has

been successfully executed, the device no longer acknowledges any instruction (with 4-bit

fixed address of 0110b) to access the write-protection settings.

X = Don’t Care

(1) Refer to Table 7 regarding the exact state of the acknowledge bit.

Fig 13. Software Write Protect (write)

A2 A1 A0

slave address (memory)

START condition

R/W acknowledge(1)

from slave

acknowledge(1)

from slave

dummy byte address

SDA

dummy data

acknowledge(1)

from slave

002aab356

STOP condition

XXXXXXXX

X = Don’t Care

(1) Refer to Table 8 regarding the exact state of the acknowledge bit.

Fig 14. Software Write Protect (read)

A2 A1 A0

slave address (memory)

START condition

R/W acknowledge(1)

from slave

no acknowledge(1)

from slave

dummy byte address

SDA

dummy data

no acknowledge(1)

from slave

002aac644

STOP condition

XXXXXXXX

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