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SE97BTP Datasheet(PDF) 16 Page - NXP Semiconductors

Part # SE97BTP
Description  DDR memory module temp sensor with integrated SPD
PDF  53 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SE97BTP Datasheet(HTML) 16 Page - NXP Semiconductors

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SE97B_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 27 January 2010
16 of 53
NXP Semiconductors
SE97B
DDR memory module temp sensor with integrated SPD
7.10.1 Write operations
7.10.1.1
Byte Write
In Byte Write mode the master creates a START condition and then broadcasts the slave
address, byte address, and data to be written. The slave acknowledges all 3 bytes by
pulling down the SDA line during the ninth clock cycle following each byte. The master
creates a STOP condition after the last ACK from the slave, which then starts the internal
write operation (see Figure 11). During internal write, the slave will ignore any read/write
request from the master.
7.10.1.2
Page Write
The SE97B contains 256 bytes of data, arranged in 16 pages of 16 bytes each. The page
is selected by the four Most Significant Bits (MSB) of the address byte presented to the
device after the slave address, while the four Least Significant Bits (LSB) point to the byte
within the page. By loading more than one data byte into the device, up to an entire page
can be written in one write cycle (see Figure 12). The internal byte address counter will
increment automatically after each data byte. If the master transmits more than
16 data bytes, then earlier bytes will be overwritten by later bytes in a wrap-around
fashion within the selected page. The internal write cycle is started following the STOP
condition created by the master.
Fig 11. Byte Write timing
002aab246
0
1
0
A2 A1 A0
0
A
S
1
A
P
slave address (memory)
START condition
R/W acknowledge
from slave
acknowledge
from slave
word address
SDA
STOP condition;
write to the memory is performed
data
DATA
A
acknowledge
from slave
Fig 12. Page Write timing
0
1
0
A2 A1 A0
0
A
S
1
A
slave address (memory)
START condition
R/W acknowledge
from slave
acknowledge
from slave
word address
SDA
data to memory
DATA n
A
acknowledge
from slave
002aab247
P
STOP condition;
write to the memory is performed
data to memory
DATA n
+ 15
A
acknowledge
from slave



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