SE97BTP datasheet(39/53 Pages) NXP

39 / 53 page

SE97B_1

Product data sheet

Rev. 01 — 27 January 2010

39 of 53

NXP Semiconductors

SE97B

DDR memory module temp sensor with integrated SPD

[1]

If the temperature sensor is not needed it should be placed in standby, which will reduce IDD(AV) to 0.1 μA typical at room temperature or

3.0

μA typical at 125 °C.

[2]

High-voltage input voltage applied to pin A0 during RWP and CRWP operations. The JEDEC specification is 7 V (min.) and 10 V (max.).

When VDD is 3.6 V, then II(ov) >4.8 V +VDD or > 4.8 V + 3.6 V then the minimum voltage is 8.4 V.

Table 31.

DC characteristics

VDD = 3.0 V to 3.6 V; Tamb = −40 °C to +125 °C; unless otherwise specified. These specifications are guaranteed by design.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD

supply voltage

3.0

3.6

IDD(AV)

average supply current

SMBus inactive

[1] -

210

320

μA

IDD

supply current

fSCL = 400 kHz

250

400

μA

Isd(VDD)

supply voltage shutdown

mode current

SMBus inactive

0.1

μA

VIH

HIGH-level input voltage

SCL, SDA

0.7

× V

-VDD +1

VIL

LOW-level input voltage

SCL, SDA

−0.5

+0.3

× V

VI(ov)

overvoltage input voltage

pin A0; VI(ov) − VDD >4.8 V

[2] 7.0

VOL

LOW-level output voltage

SDA, EVENT

IOL =0.7 mA

0.2

IOL =2.1 mA

0.4

IOL =3.0 mA

0.5

VI(hys)

hysteresis of input voltage

VDD ≥ 2.2 V

0.05

× V

VDD ≤ 2.2 V

0.10

× V

Vth(POR)H

HIGH-level power-on reset

threshold voltage

device operation voltage increase

2.9

Vth(rec)POR

power-on reset recovery

threshold voltage

device reset voltage decrease

1.2

1.8

ILOH

HIGH-level output leakage

current

EVENT; VOH =VDD

−1.0

+1.0

μA

ILIH

HIGH-level input leakage

current

SDA, SCL; VI =VDD

−1.0

+1.0

μA

ILIL

LOW-level input leakage

current

SDA, SCL; VI =VSS

−1.0

+1.0

μA

A0, A1, A2; VI =VSS

−1.0

+1.0

μA

Ci(SCL/SDA) SCL and SDA input

capacitance

-5

Ci(addr)

address input capacitance

Ipd

pull-down current

internal; A0, A1, A2 pins;

VI =0.3VDD to VDD

4.0

μA

ZIL

LOW-level input impedance

pins A0, A1, A2; VI <0.3VDD

ZIH

HIGH-level input impedance

pins A0, A1, A2; VI ≥ 0.3VDD

800

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