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6.11 DDR2/mDDR Controller

6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing

OMAP-L138 Low-Power Applications Processor

www.ti.com

SPRS586A – JUNE 2009 – REVISED AUGUST 2009

The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports

JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.

The DDR2/mDDR Memory Controller support the following features:

• JESD79D-2A standard compliant DDR2 SDRAM

• Mobile DDR SDRAM

• 512 MByte memory space for DDR2

• 256 MByte memory space for mDDR

• CAS latencies:

–

DDR2: 2, 3, 4 and 5

–

mDDR: 2 and 3

• Internal banks:

–

DDR2: 1, 2, 4 and 8

–

mDDR:1, 2 and 4

• Burst length: 8

• Burst type: sequential

• 1 chip select (CS) signal

• Page sizes: 256, 512, 1024 and 2048

• SDRAM autoinitialization

• Self-refresh mode

• Partial array self-refresh (for mDDR)

• Power down mode

• Prioritized refresh

• Programmable refresh rate and backlog counter

• Programmable timing parameters

• Little endian

Table 6-24. Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR

Memory Controller

No.

PARAMETER

1.2V

1.1V

1.0V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

DDR2

125

150

125

150

—(1)

MHz

tc(DDR_CLK)

Cycle time, DDR_CLKP / DDR_CLKN

mDDR

100

133

100

133

100

133

(1)

DDR2 is not supported at this voltage operating point.

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