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LPC3240 Datasheet(PDF) 23 Page - NXP Semiconductors |
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LPC3240 Datasheet(HTML) 23 Page - NXP Semiconductors |
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23 / 73 page ![]() LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 23 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.2.1 APB Many peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APB performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 FAB Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions. A write access to FAB peripherals takes a single AHB clock and a read access to FAB peripherals takes two AHB clocks. 7.3 Physical memory map The physical memory map incorporates several distinct regions, as shown in Figure 3. When an application is running, the CPU interrupt vectors are re-mapped to allow them to reside in on-chip SRAM (IRAM). |
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