LPC3240 datasheet(48/73 Pages) NXP

48 / 73 page

LPC3220_30_40_50_1

Preliminary data sheet

Rev. 01 — 6 February 2009

48 of 73

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

10.2 ADC static characteristics

[1]

Conditions: VSSA = 0 V (on pin VSS_AD); VDDA(3V3) = 3.3 V (on pin VDD_AD).

[2]

The ADC is monotonic; there are no missing codes.

[3]

The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 4.

[4]

The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

appropriate adjustment of gain and offset errors. See Figure 4.

[5]

The offset error (EO) is the absolute difference between the straight line which ﬁts the actual curve and the straight line which ﬁts the

ideal curve. See Figure 4.

[6]

The gain error (EG) is the relative difference in percent between the straight line ﬁtting the actual transfer curve after removing offset

error, and the straight line which ﬁts the ideal transfer curve. See Figure 4.

[7]

The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC

and the ideal transfer curve. See Figure 4.

Table 8.

ADC static characteristics

VDDA(3V3) = 3.3 V; Tamb =25°C unless otherwise speciﬁed; ADC clock frequency 4.5 MHz.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIA

analog input voltage

VDDA(3V3)

Cia

analog input capacitance

differential linearity error

[1][2][3] -

±0.5

±1

LSB

EL(adj)

integral non-linearity

[1][4] -

±0.6

±1

LSB

offset error

[1][5] -

±1

±3

LSB

gain error

[1][6] -

±0.3

±0.6

absolute error

[1][7] -

±4

LSB

Rvsi

voltage source interface resistance

Ω

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