LPC3240 datasheet(53/73 Pages) NXP

53 / 73 page

LPC3220_30_40_50_1

Preliminary data sheet

Rev. 01 — 6 February 2009

53 of 73

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

11.3 SDR SDRAM Controller

[1]

Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2]

Typical values valid for EMC pads set to high slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or low slew rate: VDD_EMC = 3.3 V,

VDD_CORE = 1.2 V.

[3]

All min or max values valid for EMC pads set to high slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or low slew rate: VDD_EMC =

3.3 V, VDD_CORE = 1.2 V.

[4]

foper = 1/tCK.

[5]

Applies to signals: EMC_DQM[3:0], EMC_DYCSm, EMC_RAS, EMC_CAS, EMC_WR, EMC_CKEm.

[6]

CMD_DLY = COMMAND_DELAY bitﬁeld in SDRAMCLK_CTRL[18:14] register, see

External memory controller (EMC) chapter in

LPC32x0 User manual.

11.4 DDR SDRAM controller

Table 11.

EMC SDR SDRAM memory interface dynamic characteristics

Tamb = −40 °C to +85 °C, unless otherwise speciﬁed.[1][3]

Symbol

Parameter

Min

Typical[2]

Max

Unit

foper

operating frequency

[4]

104

133

MHz

tCK

clock cycle time

9.6

tCL

CK LOW-level width

4.8

tCH

CK HIGH-level width

4.8

td(V)ctrl

control valid delay time

[5][6] -

(CMD_DLY

× 0.25) + 2.7

th(ctrl)

control hold time

[5][6]

(CMD_DLY

× 0.25) + 1.2

td(AV)

address valid delay time

[6] -

(CMD_DLY

× 0.25) + 3.2

th(A)

address hold time

[6]

(CMD_DLY

× 0.25) + 1.2

td(QV)

data output valid delay time

[6] -

(CMD_DLY

× 0.25) + 3.5

th(Q)

data output hold time

[6]

(CMD_DLY

× 0.25) + 1.2

tsu(D)

data input set-up time

0.6

th(D)

data input hold time

0.9

tQZ

data output high-impedance time

< tCK

Fig 7.

SDR SDRAM signal timing

002aae420

EMC_CLK

output signal (O)

input signal (I)

td(V)ctrl, td(AV), td(QV)

th(ctrl), th(Q), th(A)

th(D)

tsu(D)

tCK

tCL

tCH

tQZ

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