LPC3240 datasheet(59/73 Pages) NXP

59 / 73 page

LPC3220_30_40_50_1

Preliminary data sheet

Rev. 01 — 6 February 2009

59 of 73

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

11.8 MLC NAND ﬂash memory controller

[1]

THCLK = 1/HCLK

[2]

CEAD = bitﬁeld TCEA_DELAY[1:0] in register MLC_TIME_REG[25:24]

[3]

WL = bitﬁeld WR_LOW[3:0] in register MLC_TIME_REG[3:0]

[4]

WH = bitﬁeld WR_HIGH[3:0] in register MLC_TIME_REG[7:4]

[5]

RL = bitﬁeld RD_LOW[3:0] in register MLC_TIME_REG[11:8]

[6]

RH = bitﬁeld RD_HIGH [3:0] in register MLC_TIME_REG[15:12]

[7]

RHZ = bitﬁeld NAND_TA[2:0] in register MLC_TIME_REG[18:16]

[8]

BD = bitﬁeld BUSY_DELAY[4:0] in register MLC_TIME_REG[23:19]

Table 16.

Dynamic characteristics of the MLC NAND ﬂash memory controller

Tamb = −40 °C to +85 °C.

Symbol

Parameter

Min

Typ

Max

Unit

tCELREL

CE LOW to RE LOW time

[1][2]

-THCLK × CEAD

-ns

tRC

RE cycle time

[1][5][6]

-THCLK × (RL + 1) + THCLK × (RH − RL)-

tREH

RE HIGH hold time

[1][5][6]

-THCLK × (RH − RL)-

tRHZ

RE HIGH to output high-impedance time [1][5][7]

-THCLK × (RH − RL) + THCLK × RHZ

-ns

tRP

RE pulse width

[1][5]

-THCLK × (RL + 1)

tREHRBL

RE HIGH to R/B LOW time

[1][8]

-THCLK × BD

-ns

tWB

WE HIGH to R/B LOW time

[1][8]

-THCLK × BD

-ns

tWC

WE cycle time

[1][3][4]

-THCLK × (WL + 1) + THCLK × (WH − WL)-

tWH

WE HIGH hold time

[1][3][4]

-THCLK × (WH − WL)-

tWP

WE pulse width

[1][3]

-THCLK × (WL + 1)

Fig 15.

MLC NAND ﬂash controller write timing (writing to NAND ﬂash)

tWB

FLASH_IO[7:0]

FLASH_WR

tWP

tWC

FLASH_RDY (R/B)

FLASH_CE

10h

tWH

002aae442

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