LPC3240 datasheet(28/73 Pages) NXP

28 / 73 page

LPC3220_30_40_50_1

Preliminary data sheet

Rev. 01 — 6 February 2009

28 of 73

NXP Semiconductors

LPC3220/30/40/50

16/32-bit ARM microcontrollers

packet ﬁltering and wake-up on LAN activity. Automatic frame transmission and reception

with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can

access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces

between an off-chip Ethernet PHY using the Media Independent Interface (MII) or

Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management

(MIIM) serial bus.

7.6.2.1

Features

• Ethernet standards support:

– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,

100 Base-FX, and 100 Base-T4.

– Fully compliant with IEEE standard 802.3.

– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back

pressure.

– Flexible transmit and receive frame options.

– Virtual Local Area Network (VLAN) frame support.

• Memory management:

– Independent transmit and receive buffers memory mapped to SRAM.

– DMA managers with scatter/gather DMA and arrays of frame descriptors.

– Memory trafﬁc optimized by buffering and pre-fetching.

• Enhanced Ethernet features:

– Receive ﬁltering.

– Multicast and broadcast frame support for both transmit and receive.

– Optional automatic Frame Check Sequence (FCS) insertion with Circular

Redundancy Check (CRC) for transmit.

– Selectable automatic transmit frame padding.

– Over-length frame support for both transmit and receive allows any length frames.

– Promiscuous receive mode.

– Automatic collision back-off and frame retransmission.

– Includes power management by clock switching. Wake-on-LAN power

management support allows system wake-up using the receive ﬁlters or a magic

frame detection ﬁlter.

• Physical interface

– Attachment of external PHY chip through standard MII or RMII interface.

– PHY register access is available via the MIIM interface.

7.6.3 USB interface

The LPC3220/30/40/50 supports USB in either device, host, or OTG conﬁguration.

7.6.3.1

USB device controller

The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of register interface, serial interface engine, endpoint buffer memory and DMA

controller. The serial interface engine decodes the USB data stream and writes data to the

appropriate end point buffer memory. The status of a completed USB transfer or error

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