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LPC3240 Datasheet(PDF) 64 Page - NXP Semiconductors |
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LPC3240 Datasheet(HTML) 64 Page - NXP Semiconductors |
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64 / 73 page ![]() LPC3220_30_40_50_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 01 — 6 February 2009 64 of 73 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.10 SPI and SSP Controller 11.10.1 SPI [1] THCLK = period time of SPI IP block input clock (HCLK) Fig 19. MLC NAND flash memory status timing tCS tCH tCEA 70 h tDS tDH status tRHOH tCLS tCLH command data tCLR tCOH tREA tIR FLASH_IO[7:0] tWHR tWP tRHZ FLASH_CLE FLASH_WR FLASH_CE FLASH_RD 002aae446 Table 18. Dynamic characteristics of SPI pins on SPI master controller Tamb = −40 °C to +85 °C. Symbol Parameter Min Typ Max Unit Common to SPI1 and SPI2 TSPICYC SPI cycle time [1] 2 × THCLK - 256 × THCLK ns SPI1 tSPIDSU SPI data set-up time - 6 - ns tSPIDH SPI data hold time - 0 - ns tSPIDV SPI enable to output data valid time - 2 - ns tSPIOH SPI output data hold time - 0 - ns SPI2 tSPIDSU SPI data set-up time - 10 - ns tSPIDH SPI data hold time - 0 - ns tSPIDV SPI enable to output data valid time - 2 - ns tSPIOH SPI output data hold time - 0 - ns |
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