HCS12 datasheet(137/452 Pages) FREESCALE

137 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

137

Operation:

If (M)

• (Mask) = 0, then branch

Description:

Performs a bitwise logical AND of memory location M and the mask supplied

with the instruction, then branches if and only if all bits with a value of 1 in

the mask byte correspond to bits with a value of 0 in the tested byte. Mask

operands can be located at PC + 1, PC + 2, or PC + 4, depending on

addressing mode. The branch offset is referenced to the next address after

the relative offset (rr) which is the last byte of the instruction object code.

See 3.8 Relative Addressing Mode for details of branch execution.

BRCLR

Branch if Bits Cleared

BRCLR

CCR Details:

HIN

––––––––

Source Form

Address

Mode(1)

Object Code

Access Detail

HCS12

M68HC12

BRCLR opr8a, msk8, rel8

BRCLR opr16a, msk8, rel8

BRCLR oprx0_xysp, msk8, rel8

BRCLR oprx9,xysp, msk8, rel8

BRCLR oprx16,xysp, msk8, rel8

DIR

EXT

IDX

IDX1

IDX2

4F dd mm rr

1F hh ll mm rr

0F xb mm rr

0F xb ff mm rr

0F xb ee ff mm rr

rPPP

rfPPP

rPPP

rfPPP

PrfPPP

rPPP

rfPPP

rPPP

rffPPP

frPffPPP

1. Indirect forms of indexed addressing cannot be used with this instruction.

HCS12 Datasheet(PDF) 137 Page - Freescale Semiconductor, Inc

HCS12 Datasheet(HTML) 137 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL