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HCS12 Datasheet(PDF) 171 Page - Freescale Semiconductor, Inc |
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HCS12 Datasheet(HTML) 171 Page - Freescale Semiconductor, Inc |
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171 / 452 page  Glossary S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 171 Operation: (Y : D) ÷ (X) ⇒ Y; Remainder ⇒ D Description: Divides a signed 32-bit dividend by a 16-bit signed divisor, producing a signed 16-bit quotient and a signed 16-bit remainder. All operands and results are located in CPU registers. If an attempt to divide by zero is made, C is set and the states of the N, Z, and V bits in the CCR are undefined. In case of an overflow or a divide by zero, the contents of the registers D and Y do not change. EDIVS Extended Divide 32-Bit by 16-Bit (Signed) EDIVS CCR Details: S X HIN Z V C –––– ∆∆∆∆ N: Set if MSB of result is set; cleared otherwise Undefined after overflow or division by zero Z: Set if result is $0000; cleared otherwise Undefined after overflow or division by zero V: Set if the result was > $7FFF or < $8000; cleared otherwise Undefined after division by zero C: Set if divisor was $0000; cleared otherwise Indicates division by zero Source Form Address Mode Object Code Access Detail HCS12 M68HC12 EDIVS INH 18 14 OffffffffffO OffffffffffO |
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