HCS12 datasheet(172/452 Pages) FREESCALE

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Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

172

Freescale Semiconductor

Operation:

(M(X) : M(X+1)) × (M(Y) : M(Y+1)) + (M ~ M+3) ⇒ M ~ M+3

Description:

A 16-bit value is multiplied by a 16-bit value to produce a 32-bit intermediate

result. This 32-bit intermediate result is then added to the content of a 32-bit

accumulator in memory. EMACS is a signed integer operation. All operands

and results are located in memory. When the EMACS instruction is

executed, the first source operand is fetched from an address pointed to by

X, and the second source operand is fetched from an address pointed to by

index register Y. Before the instruction is executed, the X and Y index

registers must contain values that point to the most significant bytes of the

source operands. The most significant byte of the 32-bit result is specified

by an extended address supplied with the instruction.

EMACS

Extended Multiply and Accumulate

(Signed)

16-Bit by 16-Bit to 32-Bit

EMACS

CCR Details:

HIN

––––

∆∆∆∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00000000; cleared otherwise

V: M31

• I31 • R31 + M31 • I31 • R31

Set if result > $7FFFFFFF (+ overflow) or

< $80000000 (– underflow)

Indicates two’s complement overflow

C: M15

• I15 + I15 • R15 + R15 • M15

Set if there was a carry from bit 15 of the result; cleared otherwise

Indicates a carry from low word to high word of the result occurred

Source Form(1)

1. opr16a is an extended address specification. Both X and Y point to source operands.

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

EMACS opr16a

Special

18 12 hh ll

ORROfffRRfWWP

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