LTC3589 datasheet(29/44 Pages) LINER

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LTC3589

3589p

regulator outputs to discharge. If the PWR_ON pin is LOW

at the end of the power-down time, the LTC3589 will remain

in sleep mode with just the always-active LDO operating.

If PWR_ON is HIGH at the end of one second and the fault

condition has cleared, the LTC3589 will power-up in the

same way shown in Figure 8. Neither IRQ nor the status

registers are cleared by the fault induced shutdown.

OPERATION

ENABLE AND POWER-ON SEQUENCING

Enable Input Pin Operation

The regulator enable input pins facilitate pin-strapping an

output rail to the enable pin of the next regulator in the

desired sequence. The regulator enable inputs normally

have a 0.8V (typical) input threshold. If any enable is driven

HIGH, the remaining enable input thresholds switch to a

more accurate 500mV (typical) threshold.

Figure 11 shows an application circuit for a typical pin-

strapped start-up sequence. Holding ON LOW for 400ms

Figure 11. Pin Strap Start-Up Sequence Application Circuit

3589 F11

EN1

EN2

EN3

EN4

EN_LDO2

EN_LDO34

PWR_ON

LTC3589

PWR_ON

WAKE

SW1

SW2

SW3

BB_OUT

LDO2

LDO3

LDO4

1V TO 1.2V

1.8V

0.8V TO 1V

3.3V

1.2V

1.8V

2.8V

LDO2

LDO3

LDO4

3589 F12

WAKE

1.8V

2.8V

1.2V

3.3V

0.5V

1.8V

1.2V

200μs

Figure 12. Pin Strap Sequencing Timing

ON(PB)

PBSTAT

FAULT

WAKE

PWR_ON

CLIRQ

IRQ

3589 F10

μC/μP CONTROL

<1 SEC

Figure 10. Hard Reset Due to a Fault Condition

brings up the WAKE pin that is tied to EN1 and EN3 to

enable step-down switching regulators 1 and 3. The output

of regulator 1 is tied to EN2 and EN4 that enables step-

down switching regulator 2 and the buck-boost switching

regulator 4. The output of step-down switching regulator 2

is tied to EN_LDO2 and EN_LDO3 to enable LDO2, LDO3

and LDO4. Within ﬁve seconds of WAKE going HIGH, the

microprocessor or microcontroller must drive PWR_ON

HIGH to tell LTC3589 that rails are good and to stay in the

power-on state.

Figure 12 shows the start-up timing for the application

shown in Figure 11. There is a 200μs (typical) delay

between the enable pin and the internal enable signal to

each regulator.

Keep-Alive Operation

For systems which require an active supply rail when in

system standby, any of the three LTC3589 step-down

switching regulators or LDO2 may be kept alive regard-

less of the status of PWR_ON and WAKE. Writing a 1 to

a regulator’s keep-alive bit in its dynamic target voltage

in standby mode. A regulator with its keep-alive bit set

will stay enabled until the bit is reset writing the bit LOW,

resetting the LTC3589 with a push button hard reset, or

a fault condition (UVLO, PGOOD time out, or thermal

shutdown) occurs. PGOOD and fault status are reported

in the IRQSTAT and PGSTAT registers and on the IRQ and

PGOOD pins for keep-alive regulators when PWR_ON and

WAKE are LOW.

LTC3589 Datasheet(PDF) 29 Page - Linear Technology

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