TLK6002 datasheet(6/96 Pages) TI

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RDB_[19:0]

RXCLK_B

S/W

3.9

S/W

{3.9,3.8}

RX A FIFO

RXBFIFO

RDA_[19:0]

TXBCLK_B

RXBCLK_B

TXBCLK_A

RXBCLK_A

RXCLK_A

S/W

{3.9,3.8}

TXBCLK_A

RXBCLK_A

TXBCLK_B

RXBCLK_B

S/W

3.9

RXDB_INT[9:0]

RXBCLK_B

RXDA_INT[9:0]

RXBCLK_A

TX A Datapath

CH A RX

Datapath

RXDA[9:0]

RXBCLK_A

TX A Datapath

Channel A

RXSERDES

TX A Datapath

CHBRX

Datapath

RXDB[9:0]

RXBCLK_B

TX A Datapath

ChannelB

RXSERDES

= PrimaryDevicePin

S/W

x.x:x

Legend:

= SoftwareProgrammable / Register Address.Bit

RXBCLK_*, TXBCLK_* frequencyisSerialBitRateDividedby 10

DDR:

SDR:

DDR:

SDR:

614.4 /

1228. 8 /

2457. 6 /

3072 /

4915. 2 /

6144 Mbps

Line rates for CPRI

Line rates for OBSAI

768 /

1536 /

3072 /

6144Mbps

LO _ 1

Duplexer

LNA

ADC

12- bit

ADC

IF 1

IF 2

61. 44 MHz

TLK 6002

( Serdes

TLK6002

TLK3131 /

32 /34

Serdes

CPRI /

OBSAI

ADS5232

ADS5240

ADS528 x

61.44 MHz

245.76 MHz

DAC5682 z

DAC 5688

DAC 5687

LO _ 1

16 - bit

DAC

FIR

16 - bit

DAC

FIR

DDC

GC 6016

I / Q

61. 44 MHz

CDCEX52005

X - tal

FPGA

TX _CLK

I/Q

DUC

GC 6016

FPGA

RX_CLK

TLK6002

SLLSE34 – MAY 2010

www.ti.com

Figure 1-5. TLK6002 Receive Clock Architecture

Figure 1-6. TLK6002 Application Diagram

Introduction

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