TLK6002 datasheet(72/96 Pages) TI

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TXCLK_x

TDx

VIH(ac)

VDDQ/2

VIL(ac)

VIH(ac)

VDDQ/2

VIL(ac)

tPERIOD

tSETUP

tHOLD

tSETUP

tHOLD

TXCLK_x

TDx

VOH(ac)

VDDQ/2

VOL(ac)

VOH(ac)

VDDQ/2

VOL(ac)

TSKEW

TLK6002

SLLSE34 – MAY 2010

www.ti.com

4.12

HSTL (DDR Timing Mode Only) Input Timing Requirements

PARAMETER

CONDITION

MIN

MAX

UNIT

TDx(1) setup prior to TXCLK_x(2) transition high

Source Centered, See Figure 4-16

tsetup

0.075 × tperiod

or low

and (3)

Source Centered, See Figure 4-16

thold

TDx hold after TXCLK_x transition high or low

0.075 × tperiod

and (3)

Source Centered, See Figure 4-16

40%

60%

and (3)

tduty

TXCLK_x Duty Cycle

Source Aligned, See Figure 4-17

45%

55%

and (3)

tperiod

TXCLK_x Period

Source Centered and Aligned

6.4

85.11

Tfreq

TXCLK_x Frequency

Source Centered and Aligned

11.75

156.25

MHz

Tskew

(4) (5

Source Aligned, See Figure 4-17

TXCLK_x rising or falling to TDx valid.

–0.14 × tperiod

+0.14 × tperiod

)

and (3)

(1)

TDx refers to either channel A (TDA) or B (TDB).

(2)

TXCLK_x refers to either channel A (TXCLK_A) or channel B (TXCLK_B).

(3)

Input timing reference of (VDDQA/B)/2 with ±1 ns/V rise time on all input signals.

(4)

When Tfreq ≤60 MHz, Tskew Minimum is –3ns.

(5)

When Tfreq ≤60 MHz, Tskew Maximum is 3ns.

Figure 4-16. HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements

Figure 4-17. HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements

ELECTRICAL SPECIFICATIONS

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