6402 datasheet(77/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

SMBus Interface

The Intel 6400/6402 Advanced Memory Buffer (AMB) has configuration registers that

provide flexibility and allow for testing and optimization of the chip. Upon system reset

(RESET#), configuration registers are reset to predetermined default states,

representing the minimum feature set required to successfully bring up a nominal

channel. It is expected that the BIOS will properly determine and program the optimal

configuration settings.

For all of these registers, the AMB supports register access mechanisms through SMBus

as well as through in-band channel commands.

7.1

System Management Access

System Management software in the platform can initiate system management access

to the configuration registers. This can be done through SMBus accesses.

The mechanism for the Server Management (SM) software to access configuration

registers is through a SMBus Specification, Rev. 2.0-compliant slave port. The AMB

contain this slave port and allow access to the configuration registers.

SMBus operations are made up of two major steps: (1) writing information to registers

within each component and (2) reading configuration registers from each component.

The following sections will describe the protocol for an SMBus master to access a AMB’s

internal configuration registers. Refer to the SMBus Specification, Rev. 2.0 for the bus

protocol, timings, and waveforms.

7.1.1

SMBus 2.0 Specification Compatibility

The principal requirement from the SMBus 2.0 specification is support of the “high

power” bus electrical specifications described in the layer 1 (Physical layer) chapter.

For the simple register access requirements of FBD, no layer 2 (Link layer) or layer 3

(Network layer) extensions provided by the 2.0 specification are used. In particular,

there is no support for Address Resolution Protocol (ARP) since FBD is using fixed

addresses. Additionally, only a subset of the network packet protocols described in the

specification are needed and these are described below.

AMB’s are required to support read and write transactions without requiring clock

stretching in order to simplify host controller requirements. For similar reasons, AMB’s

should not master SMBus transactions in normal operation.

7.1.2

Supported SMBus Commands

The AMB SMBus Rev. 2.0 slave ports support register reads and writes built out of the

following SMBus primitive commands:

The slave address for each primitive SMBus transaction are determined from the SA

pins.

• For normal FBD DIMMs:

— Slave Address[6:3] = 4’b1011

— Slave Address[2:0] = SA[2:0]

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