6402 datasheet(94/250 Pages) INTEL

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Reset

Intel® 6400/6402 Advanced Memory Buffer Datasheet

• These “Next” register values must be transferred to the matching “Current”

registers before the FBD link leaves the DISABLE state

— Updates may be done right after the NXT register is updated when link is in

electrical idle. Updates must be complete before the beginning of training.

7. FBD Link is initialized including CALIBRATION state.

8. Remaining AMB configuration is loaded over high speed FBD channel

• CMD2DATA, remaining personality bytes, other SPD parameters, DRAM

parameters, Errors enabled, and so forth.

9. FBD Link goes through fast reset (no CALIBRATION) to establish the desired

configuration

10. DRAM interface can now be established

a. MRS/EMRS setup using DCALCSR and DCALADDR

b. DRAM interface calibrated using DCALCSR

c. Optionally, MemBIST functionality can be used to test the DRAMs

d. DRAM’s can be initialized using MemBIST

11. Refresh must now be transferred to the host

• Option 1: Use fast reset on the link with DRAMs in self-refresh

— clear DSREFTC:DISSREXIT to enable fast self refresh exit when link is re-

established

— put the link in disable state which automatically puts the DRAMs in self refresh.

— Start the refresh engine on the host

— bring up the link again

— Host starts sending refresh commands as soon as L0 state reached

• Option 2: write control register to disable auto-refresh engine followed by

— Clear DAREFTC:AREFEN to turn off auto-refresh

— Host then immediately takes over sending refresh commands

12. Host now has complete control of the FBD Channel

9.4.2

S3 Restore Power-Up Reset Sequence

Follow steps 1) through 9) from cold power up sequence above. Step 2, BIOS query of

SPD may be skipped if these values are saved elsewhere. Either way the personality

bytes from the SPD are restored to their prior values in the AMB. Once this is done the

DRAM interface can be restored.

1. DRAM interface can now be restored

a. DRC, MTR, DSREFTC, and DAREFTC register restored

b. Stored S3RESTORE[15:0] are written back into each AMB

— do NOT recalibrate the DRAM interface using DCALCSR

— do NOT reinitialize the DRAMs using MemBIST

2. Refresh must now be transferred to the host as in cold power up

3. Host now has complete control of the FBD Channel and prior DRAM memory state

has been preserved.

6402 Datasheet(PDF) 94 Page - Intel Corporation

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