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FBD Channel Interface

Intel® 6400/6402 Advanced Memory Buffer Datasheet

the data driven to the subsequent DIMMs is re-sampled in the AMB to reduce jitter. The

lowest latency implementation would use the derived clock to retransmit the outbound

signal. The second DIMM will see the phase shift as a slight change in the position of

the data eye at its receiver. The clock tracking loop filter in the second DIMM will

measure several bit cells and may eventually determine that it should adjust the phase

of its derived clock to capture the data closer to the center of the new data eye

location. Only when the second DIMM makes its phase change will the effect propagate

to the third DIMM. More detail of the data sampling technique may be found in the

“High Speed Differential Point-to-Point Link at 1.5V for Fully Buffered DIMM

Specification”.

2.5.1.2

Accumulated Tracking Effects (Re-Sync Option)

An alternative implementation would place a voltage/thermal (VT) drift compensation

buffer between the receiver and the transmitter section of the AMB I/O cell. The drift

compensation buffer would re-synchronize the signal with a multiple of the reference

clock. This buffer would have to be deep enough to handle the absolute magnitude of

delay change of the daisy-chain channel over voltage and temperature. More detail of

the data sampling technique may be found in the “High Speed Differential Point-to-

Point Link at 1.5V for Fully Buffered DIMM Specification”.

2.5.2

Other Channel Configuration Modes

Other channel electrical configuration parameters that should be set up prior to link

initialization include

• Link frequency (LINKPARNXT.CFREQ)

• SB Transmitter drive current (FBDSBCFGNXT.SBTXDRVCUR)

• SB Transmitter de-emphasis values (FBDSBCFGNXT.SBTXPREEMP)

• NB Transmitter drive current (FBDNBCFGNXT.NBTXDRVCUR)

• NB Transmitter de-emphasis values (FBDNBCFGNXT.NBTXPREEMP)

The parameters contained in these registers are described more completely in the

“High Speed Differential Point-to-Point Link at 1.5V for Fully Buffered DIMM

Specification”.

Additional channel configuration registers that should be set up prior to link

initialization include

• First 6 bytes of the SPD parameter registers

— SPDPAR01NXT,SPDPAR23NXT,SPDPAR45NXT

• FBD Bit Lock Time Out Register (FBDLOCKTO)

2.5.3

Lane to Lane Skew on a Channel

The FBD Channel is expected to support a maximum skew of up to 46UI. The deskew

buffers on an individual AMB need to be able to support this amount of accumulated

skew. The actual skew observed will be a function of the skew introduced by platform

layout, DIMM layout, the number of active AMBs in the channel and skew introduced by

AMBs.

6402 Datasheet(PDF) 20 Page - Intel Corporation

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