6402 datasheet(100/250 Pages) INTEL

100 / 250 page

Transparent Mode

100

Intel® 6400/6402 Advanced Memory Buffer Datasheet

Data from the tester is 16 bits wide at 200 MHz (single data rate). The data rate is

doubled and the width halved on the way to the DRAM (by clocking out 8 bits of data on

the rising edge of the clock and the remaining 8 bits on the falling edge).

The tester will drive data to be written to the DRAM on a write pass and data to be

compared on a read. DRAM data and the expected data from the tester is compared in

the AMB. If the actual and expected data differ the pass/fail outputs will indicate which

DRAM failed.

10.1.1

Block Diagram

The data paths for transparent mode will bypass all link logic and normal DRAM control

logic. The DDR interfaces are used intact. Figure 10-2 is a block diagram of the Intel

6400/6402 Advanced Memory Buffer (AMB) in transparent mode.

10.1.2

Transparent Mode Signal Definitions

When the transparent mode is enabled. The FBD (Fully-Buffered DIMM) differential

input pins designed in the AMB part become two single ended inputs. In transparent

mode the FBD input pins require 0 to 500 mV swing (half of the normal differential

input voltage). Input slew rates should be approximately 5 V/ns. This parameter is not

critical, but it must be fast enough to be recognized by the AMB receiver. The DDR pins

will operate with normal DDR2 timings and levels.

The AMB clock input pins will be used for transparent mode as well as normal mode.

This also allows use of most of the existing on-chip clock distribution network.

Figure 10-2. Block Diagram for the AMB in transparent mode

SET

CLR

SET

CLR

SET

CLR

SET

CLR

SET

CLR

TCMD/TADD

TDRV

TDQ

Status

DRAM CMD/ADD

SET

CLR

SET

CLR

ENB

CENB

Multiplexer

DFTDATA

DRAMWR

DRAM DQ

DDR IO Read

Data FIFO

SET

CLR

Shift Register

Controlled by AMB CL, AL, CMD2DATA

or hard coded to RL=4 and CMD2DATA=4

ENB

Multiplexer

Shift Register

Controlled by AMB CL, AL

or hard coded for WL=3

TCMP

Read Pointer

ENDOUT, DRAMRD

SET

CLR

ENB

DRAM DQS

144

ENB

6402 Datasheet(PDF) 100 Page - Intel Corporation

6402 Datasheet(HTML) 100 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL