6402 datasheet(101/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

101

Transparent Mode

10.1.3

Transparent Mode to FBD Pin Mapping

The FBD pin mapping is shown in Table 10-2.

Table 10-1. Additional Signals in Transparent Mode

Transparent

Mode Signal

Name

Pin Count

Frequency

Direction

Definition

TCKE[1:0]

200 MHz

Controls CKE[1:0]{A,B}

TCS#[1:0]

200 MHz

TODT

200 MHz

Controls both ODT[1:0]{A,B}

TRAS#

200 MHz

TCAS#

200 MHz

TWE#

200 MHz

Controls WE{A,B}

TBA[2:0]

200 MHz

TA[14:0]

200 MHz

TDRV

200 MHz

Tester signal to drive data on writes

TCMP

200 MHz

Tester signal to compare on reads

TDQ[15:8]

200 MHz

Early data to each byte

TDQ[7:0]

200 MHz

Late data to each byte

TPF[8:0] or

TDQO[15:0]

9 or 16

200 MHz

Out

Used for pass/fail (8:0) or direct access (15:0)

Sum of receivers

Sum of drivers

Table 10-2. Mapping of FBD Pins in Transparent Mode

FBD Pin Name

Count

Speed

Transparent Mode Signal

Name

Comment

SN[0], SN[0]

200 MHz

TCKE[1:0]

SN[1], SN[1]

200 MHz

TCS#[1:0]

SN[2],

200 MHz

TODT

SN[2]

200 MHz

TRAS#

SN[3],

200 MHz

TCAS#

SN[3]

200 MHz

TWE#

SN[4], SN[4]

SN[5]

200 MHz

TBA[2:0]

SN[13:6], SN[13:6]

200 MHz

TA[15:0]

PS[8]

200 MHz

TDRV

PS[8]

200 MHz

TCMP

PS[7:0]

200 MHz

TDQ[15:8]

Early data

PS[7:0]

200 MHz

TDQ[7:0]

Late data

SS[8:0]

200 MHz

TPF[8:0]

Pass/Fail mode

(TRANSCFG.ENDOUT =0)

PN[13:7],

SS[8:0]

200 MHz

TDQO[15:0]

Data output mode

(TRANSCFG.ENDOUT =1)

Total Pins

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