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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Clocking

8.2

PLL Clocks

The PLL receives a reference clock at 1/2X, where X is the DDR command frequency.

The PLL generates the internal clocks shown below in Table 8-1.

There are additional PLL modes used for testing and bring up. Details are in Section

8.9, “Additional Clock Modes” on page 87.

8.3

Reference Clock

A low-jitter differential reference clock (REFCLK) is routed to the host and each DIMM

from a common clock source on the system board. This reference clock uses HCSL

(High-Speed Current Steering Logic) signaling and its detailed requirements are

documented in the FB-DIMM Draft Specification: High Speed Differential P2P Link at

1.5V. The AMB uses the reference clock to generate internal buffer clocks and to

generate the clocks to the DRAMs located on each DIMM. The frequency of the

reference clocks (133 to 200 Mhz) is one half the frequency of the DRAM base clock

(267 to 400 Mhz), that is, it is one half the command-rate of the DRAM devices located

behind the AMB. For example, for DDR2 667 DRAM devices the reference clock

frequency would be 167 MHz. The reference clock is the basis for the various Core, FBD

and DDR internal clocks.

It is a requirement for the FBD channel to operate in the presence of Spread Spectrum

Clocking (SSC), which is commonly used to reduce EMI. The reference clocks for FBD

have to meet a jitter specification.

The reference clocks to the host and each DIMM are mesochronous, that is, they have

an unknown but fixed phase relationship to each other or the memory channel. This

simplifies PCB routing since no precise length matching is required. However an upper

bound for the clock length mismatch is necessary since the maximum phase difference

between the data sent out with the transmitter clock and the receiver clock needs to be

limited in the presence of SSC. It is required that all the reference clocks for a given

FBD channel originate from a single clock source, for example, a common clock

synthesizer or clock oscillator, and travel through the same jitter spectrum modifying

components (for example, PLL clock buffer) thereby ensuring that there is no frequency

mismatch or frequency drift between FBD agents.

Table 8-1.

PLL Clocks

Clock

Notes

DDRCA1X

This clock is unused in the AMB. It is still used for setting the alignment of the DDRCA2X clock

within the PLL.

DDRCA2X

Rising edge aligned to DDRCA1X. Also allows command/address bus to run at DDR data rate

in LAI mode.

DDR1X

Along with DDR2X and DDR2X#, used by DDRI/O cluster to generate DDR command clock,

DDR DQS output, and DDR DQ output. This is also used as core clock.

DDR2X

Rising edge aligned to DDR1X

DDR2X#

Inverted DDR2X

DDRRD1X

Used by DDRI/O cluster to advance the DDR Read FIFO read-pointer. It is also by Northbound

logic. This is driven by an independent divider and can be moved w.r.t to the core clock in 2UI

increments to align it with the DDR data availability.

HVMCLK

This is a fixed clock at the same frequency as the core clock but is driven by a independent

divider.

FBDCK (4)

Four phases of 6X clock. Provided to FBD Northbound, Southbound high-speed I/O clusters.

These signals are connected by abutment.

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