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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Reset

9.3.2

Primary FBD Link

When an EI occurs on the primary southbound FBD link a fast reset is started. This

starts a handshake procedure putting the DRAMs into self-refresh mode and resetting

the AMB. Fast reset does not reset the PLL, sticky flops, and sticky configuration

registers.

9.4

Details

Reset details and sequences will be released in a future revision of this document.

9.4.1

Cold Power-Up Reset Sequence

1. 1.5 V, 1.8 V and 3.3 V power supplies comes up

• RESET# asserted low while power supplies are coming up

• CKE’s are low upon 1.8 V power up

2. BIOS queries SPD on all the FBDs on the channel to determine operating conditions

— channel frequency, compatible DIMMs, DRAM and AMB parameters

3. Clocks up and stable at required frequency

• Reference Clocks (SCK/SCK) should be stable at least 1ms before RESET#

deasserted for designs with PLL running independent of RESET#

• DRAM clocks (CLK/CLK) may be toggling at this time

4. RESET# deasserted high

• CKE’s to DRAMs remain low

5. No transactions for at least 200 us after RESET# deasserted for designs with PLL’s

tied to RESET#

• No SMBus or in-band activity during this period

• DRAM clocks should be stable at this time

6. AMB parameters critical for robust link initialization are programmed via SMBus

• Architected link registers

— LINKPARNXT: link frequency - Note: some AMBs may use this write to trigger

PLL init

— FBDSBCFGNXT: SB transmitter drive strength, de-emphasis setting and pass-

thru mode

— FBDNBCFGNXT:NB transmitter drive strength, de-emphasis setting and pass-

thru mode

— FBDBLTO:if NB lanes are to be deconfigured

• Personality Bytes from SPD needed for link initialization

— PERSBYTE[5:0]NXT:

In the AMB, these match:

— SPDPAR01NXT: various FBD IO implementation specific controls

— SPDPAR23NXT:various FBD IO implementation specific controls

—SPDPAR45NXT

— remaining Personality bytes are not required for link init and may be loaded

over the high speed FBD configuration register accesses

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