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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Reset

This chapter describes aspects of hardware reset specific to the Intel 6400/6402

Advanced Memory Buffer (AMB).

9.1

Platform Reset Functionality

The FBD channel provides a RESET# signal to initialize all AMBs on the channel. The

generation of this signal is platform dependent, and may be asynchronous to the clock.

The platform will assert RESET# at power up. This signal may be asserted at other

times, such as a warm boot.

It is possible that platform conditions cause RESET# to be asserted at any time,

including in the middle of DRAM commands. This could occur during a warm boot.

Under these conditions, the AMB will be reset and the contents of memory are not

guaranteed. The state of the DRAMs must be guaranteed when reinitialized for proper

response.

9.1.1

Platform RESET# Requirements

• RESET# must be asserted at power up, and may also be asserted at other times

such as a warm boot. Asserting RESET# at warm boot will clear all error logging

registers.Asserting RESET# only at power up will allow error logging registers to be

maintained through a warm boot cycle.

• Asserting RESET# at warm boot will clear all error logging registers.

There is no need to delay or lockout RESET# going to the FBD channel since the AMB

will guarantee that the tDelay parameter is met. Reference Clocks must remain stable

for at least 4 clock cycles after RESET# is asserted in order to allow the AMB to satisfy

the tDelay requirement.

• RESET# must be asserted during power up, and for a minimum of 1 mS after the

FBD channel power and reference clocks SCK/SCK are stable.

• RESET# must be asserted for a minimum of 100 uS. This will only apply if RESET#

is re-asserted while power and clocks remain stable.

• After initial power on, if the reference clock frequency is changed while Reset is

asserted, reset must not be deasserted until power and reference clocks SCK/SCK

have been stable for at least 1 ms.

9.1.2

RESET# Requirements

RESET# is asynchronously applied to all storage elements. Assertion of RESET# does

not effect AMB PLL operation. Internal clocks continue to run.

Upon assertion of RESET#:

• DRAM CKE is driven low asynchronously with minimal delay (within 1 clock, asynch

path from reset to CKE).

•DRAM CLK/CLK continue to run with no short pulses generated within the tDelay

period specified in JEDEC ballot 1410.01.

•DRAM CLK/CLK may be stopped after the tDelay has been satisfied.

6402 Datasheet(PDF) 91 Page - Intel Corporation

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