E6000 datasheet(32/122 Pages) INTEL

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Electrical Specifications

Datasheet

2.7.7

Phase Lock Loop (PLL) and Filter

An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is

used for the PLL. Refer to Table 5 for DC specifications.

2.7.8

BCLK[1:0] Specifications (CK505 based Platforms)

Table 17.

BSEL[2:0] Frequency Table for BCLK[1:0]

BSEL2

BSEL1

BSEL0

FSB Frequency

266 MHz

RESERVED

200 MHz

RESERVED

333 MHz

Table 18.

Front Side Bus Differential BCLK Specifications

Symbol

Parameter

Min

Typ

Max

Unit Figure Notes1

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Input Low Voltage

-0.30

N/A

2. "Steady state" voltage, not including overshoot or undershoot.

Input High Voltage

N/A

1.15

VCROSS(abs) Absolute Crossing Point

0.300

N/A

0.550

4, 5

3, 4, 5

3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0

equals the falling edge of BCLK1.

4. VHavg is the statistical average of the VH measured by the oscilloscope.

5. The crossing point must meet the absolute and relative crossing point specifications

simultaneously.

ΔVCROSS

Range of Crossing Points

N/A

0.140

4, 5

VOS

Overshoot

N/A

1.4

6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as

the absolute value of the minimum voltage.

VUS

Undershoot

-0.300

N/A

VSWING

Differential Output Swing

0.300

N/A

7. Measurement taken from differential waveform.

ILI

Input Leakage Current

-5

N/A

μA

Cpad

Pad Capacitance

.95

1.2

1.45

8. Cpad includes die capacitance only. No package parasitics are included.

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