E6000 datasheet(97/122 Pages) INTEL

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Features

The system can generate a STPCLK# while the processor is in the HALT powerdown

state. When the system de-asserts the STPCLK# interrupt, the processor will return

execution to the HALT state.

While in HALT Power powerdown, the processor processes bus snoops.

6.2.2.2

Extended HALT Powerdown State

Extended HALT is a low power state entered when all processor cores have executed

the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.

When one of the processor cores executes the HALT instruction, that logical processor

is halted; however, the other processor continues normal operation. The Extended

HALT Powerdown state must be enabled via the BIOS for the processor to remain within

its specification.

The processor automatically transitions to a lower frequency and voltage operating

point before entering the Extended HALT state. Note that the processor FSB frequency

is not altered; only the internal core frequency is changed. When entering the low

power state, the processor first switches to the lower bus ratio and then transitions to

the lower VID.

While in Extended HALT state, the processor processes bus snoops.

The processor exits the Extended HALT state when a break event occurs. When the

processor exits the Extended HALT state, it will resume operation at the lower

frequency, transitions the VID to the original value and then changes the bus ratio back

to the original value.

6.2.3

Stop Grant and Extended Stop Grant States

The processor supports the Stop Grant and Extended Stop Grant states. The Extended

Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer

to the following sections for details about the Stop Grant and Extended Stop Grant

states.

6.2.3.1

Stop Grant State

When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered

20 bus clocks after the response phase of the processor-issued Stop Grant

Acknowledge special bus cycle.

Since the GTL+ signals receive power from the FSB, these signals should not be driven

(allowing the level to return to VTT) for minimum power drawn by the termination

resistors in this state. In addition, all other input signals on the FSB should be driven to

the inactive state.

RESET# causes the processor to immediately initialize itself, but the processor will stay

in Stop Grant state. A transition back to the Normal state occurs with the de-assertion

of the STPCLK# signal.

A transition to the Grant Snoop state occurs when the processor detects a snoop on the

FSB (see Section 6.2.4).

While in the Stop Grant State, SMI#, INIT#, and LINT[1:0] is latched by the processor,

and only serviced when the processor returns to the Normal State. Only one occurrence

of each event will be recognized upon return to the Normal state.

While in Stop Grant state, the processor processes a FSB snoop.

E6000 Datasheet(PDF) 97 Page - Intel Corporation

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