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GC5337 Datasheet(PDF) 38 Page - Texas Instruments |
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GC5337 Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 49 page  GC5330 GC5337 SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 19. RX ADC-W14 Switching Characteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT RX input clock frequency ADCA14 Clk, fCLK(ADC) See (1) 620 MHz ADCB14 Clk tsu(ADC,A) Input data setup time on port A before See (1)(2) 160 ps ADCA14 Clk transition th(ADC,A) Input data hold time on port A after See (1)(2) 200 ps ADCA14 Clk transition tsu(ADC,B) Input data setup time on port B before See (1)(2) 180 ps ADCB14 Clk transition th(ADC,B) Input data hold time on port B after See (1)(2) 220 ps ADCB14 Clk transition (1) Chip specifications are production tested at 90 °C case temperature for the given specification. Early production lots are sample tested at –40°C. (2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing. Table 20. RX ADC-B7, B14 Switching Characteristics PARAMETER TEST CONDITIONS MIN NOM MAX UNIT fCLK(ADC-AB) RX input clock frequency, ADCA7 Clk, See (1) 620 MHz ADCB7 Clk fCLK(ADC-C) RX input clock frequency, ADCC7 Clk See (1) 620 MHz Input data setup time on port A before tsu(ADC,A) See (1)(2) 260 ps ADCA7 Clk transition Input data hold time on port A after th(ADC,A) See (1)(2) 160 ps ADCA7 Clk transition Input data setup time on port B before tsu(ADC,B) See (1)(2) 170 ps ADCB7 Clk transition Input data hold time on port B after th(ADC,B) See (1)(2) 140 ps ADCB7 Clk transition Input data setup time on port C before tsu(ADC,C) See (1)(2) 290 ps ADCC7 Clk transition Input data hold time on port C after th(ADC,C) See (1)(2) 150 ps ADCC7 Clk transition Input data setup time on port A before tsu(ADC,A) See (1)(2) 130 ps ADCA14 Clk transition Input data hold time on port A after th(ADC,A) See (1)(2) 200 ps ADCA14 Clk transition Input data setup time on port B before tsu(ADC,B) See (1)(2) 170 ps ADCB14 Clk transition Input data hold time on port B after th(ADC,B) See (1)(2) 240 ps ADCB14 Clk transition (1) Chip specifications are production tested at 90 °C case temperature for the given specification. Early production lots are sample tested at –40°C. (2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing. 38 Submit Documentation Feedback © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): GC5330 GC5337 |
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