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GC5337 Datasheet(PDF) 43 Page - Texas Instruments |
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GC5337 Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 49 page ![]() CEB Addr OEB WEB Data T0518-01 t su(WR) t su(WR) t su(WR) t h(WR) t h(WR) t h(WR) t high(WR) t low(WR) GC5330 GC5337 www.ti.com SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011 Figure 27. MPU WRITE Timing Specifications Power Sequencing Guideline TI ASIC I/O design allows either the core supply (VDD) or the I/O supply (VDDS) to be powered up(2) for an indefinite period of time while the other power supply is not powered up, if all of these constraints are met: • Chip is within all maximum ratings and recommended operating conditions. • Have followed all warnings about exposure to maximum rated and recommended conditions, particularly junction temperature. These apply to power transitions as well as normal operation. • Bus contention while VDDS is powered up must be limited to 100 hours over the projected lifetime of the device. • Bus contention while VDDS is powered down may violate the absolute maximum ratings. However, it is generally good practice to power up VDD, VDDSHV, and VDDS all within 1 second of each other. Application Information The GC533x reference design includes the following additional transmit/receive signal chain components: • TMS320C6748 digital signal processor (DSP) and DPD adaptation software • DAC3283 16-bit 800-MSPS, dac348X, or DAC5682 16-bit, 1-GSPS DAC (transmit path) • CDCE72010 clock generator • TRF3720 300-MHz to 4.8-GHz quadrature modulator with integrated wideband PLL/VCO • TRF370317 0.4-GHz to 4-GHz quadrature modulator • ADS41B49 14-bit, 250-MSPS ADC (and other options; feedback path) • AMC7823 analog monitoring and control circuit with GPIO and SPI • PGA870 wideband programmable gain amplifier • ADS42b49 14-bit dual 250-MSPS receive or complex feedback ADC (and other options; RX path) MPU Interface Guidelines The following section describes the hardware interface between the recommended microprocessor and the GC533x. The GC533x interface is an EMIF asynchronous interface. (2) A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that range, either stable or in transition. © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Link(s): GC5330 GC5337 |
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