GC5337 datasheet(31/49 Pages) TI

31 / 49 page

BBIN Data, BBIN Sync

BBIN Clk

T0507-01

GC5330

GC5337

www.ti.com

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

Table 11. General Switching Characteristics, TX BB LVDS Input

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

BASEBAND INTERFACE DDR LVDS

fCLK(BB-Serial)

384

500(Nibble0)

fCLK(BB-Nibble)

Baseband input clock frequency

See (1)

MHz

384(Nibble1)

fCLK(BB-Byte)

384

fCLK(RXA)

Baseband input clock frequency, using RXA

See (1)

250

MHz

tsu(BBS0)

BBIN3 Clk, BBIN1:0 Data, BBIN2 Sync

See (1)(2)

250

thi(BBS0)

BBIN3 Clk, BBIN1:0 Data, BBIN2 Sync

See (1)(2)

200

tsu(BBS1)

BBIN7 Clk, BBIN5:4 Data, BBIN6 Sync

See (1)(2)

210

thi(BBS1)

BBIN7 Clk, BBIN5:4 Data, BBIN6 Sync

See (1)(2)

250

tsu(BBS2)

BBIN11 Clk, BBIN9:8 Data, BBIN10 Sync

See (1)(2)

240

thi(BBS2)

BBIN11 Clk, BBIN9:8 Data, BBIN10 Sync

See (1)(2)

190

tsu(BBN0)

BBIN3 Clk, BBIN5,4,1,0 Data, BBIN2 Sync

See (1)(2)

250

th(BBN0)

BBIN3 Clk, BBIN5,4,1,0 Data, BBIN2 Sync

See (1)(2)

220

tsu(BBN1)

BBIN7 Clk, BBIN11:8 Data, BBIN6 Sync

See (1)(2)

250

th(BBN1)

BBIN7 Clk, BBIN11:8 Data, BBIN6 Sync

See (1)(2)

220

tsu(BB)

BBIN7 Clk, BBIN11:8,5:4,2:0 Data, BBIN6 Sync

See (1)(2)

280

th(BB)

BBIN7 Clk, BBIN11:8,5:4,2:0 Data, BBIN6 Sync

See (1)(2)

250

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

–40°C.

(2)

Setup and hold times are measured from differential data crossing zero to differential clock crossing zero.

Figure 15. TX Baseband LVDS Input Timing Specifications

The BB LVDS RX outputs have three different output timing modes, DDR0, DDR1 and DDR2. DDR1 and DDR2

modes output data, and the BBclk output is centered over the data. In DDR0 mode, the data and clock are

edge-aligned. Different BBOUT pins are used for clock, frame, and data pins depending on the byte, nibble, and

serial modes. The DDR1 and DDR2 modes are shown in Table 12 and Figure 16. The DDR0 mode is shown in

Table 13 and Figure 17. Table 12 and Figure 16. DDR1 mode is used upto a BBclk frequency of 310 MHz.

DDR2 mode is used upto a BBclk frequency of 155 MHz. When the data rate is higher than 500 MHz, BBclk

above 250 MHz, the operating mode is DDR0. In this mode, the clock is aligned with the output data transition. In

DDR0 mode, the customer must delay the clock to meet the tsu and thi target for the baseband input. The tskw

time is measured as the relative skew for the data and frame to the clock output. This is shown in Figure 13 and

Table 17.

In receive (uplink) mode, the GC5330 outputs data using the LVDS pins BBOUT. The BBOUT port may be

operated in three modes, DDR0, DDR1, and DDR2.

Submit Documentation Feedback

Product Folder Link(s): GC5330 GC5337

GC5337 Datasheet(PDF) 31 Page - Texas Instruments

GC5337 Datasheet(HTML) 31 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

Datasheet Download

Link URL