GC5337 datasheet(32/49 Pages) TI

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BBOUT Data

BBOUT Sync

BBOUT Clk

T0508-01

GC5330

GC5337

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

www.ti.com

The lowest-rate outputs use DDR2 mode, where the output clock changes on one rising edge of the internal

clock and the output data changes on the subsequent rising edge. In DDR2 mode, the output bit rate (per LVDS

pair) is half of the internal clock. Middle-rate outputs use DDR1 mode, where the output clock changes on the

falling edge of the internal clock and the output data changes on the rising edge of the internal clock, which

results in an output bit rate equal to the internal clock rate. Both DDR1 and DDR2 result in the output clock edge

occurring in the middle of output data-stable time. The DDR1 and DDR2 modes are shown in Table 12 and

Figure 16.

The highest-rate outputs use DDR0 mode, where both the output clock and output data change with both the

rising and falling edges of the internal clock. The DDR0 output bit rate is twice the internal clock rate. DDR0

results in the clock and data changing at the same time, and typically requires extra trace length on the PC board

for the clockout signal to provide the required setup time for the receiving chip. The DDR0 mode is shown in

Table 13 and Figure 17.

Table 12. General Switching Characteristics, RX BB LVDS Output

– DDR1, DDR2

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

BASEBAND INTERFACE DDR LVDS

fCLK(BB-DDR2)

See (1). Applies to BBOUT byte,

155

Baseband output clock frequency

MHz

nibble, or serial

fCLK(BB-DDR1)

310

tskmin(BB)Serial0

BBOUT3 Clk, BBOUT1:0 Data, BBOUT2 Sync

See (2)(3)

–20

tskmax (BB)Serial0 BBOUT3 Clk, BBOUT1:0 Data, BBOUT2 Sync

See (2)(3)

350

tskmin(BB)Serial1

BBOUT7 Clk, BBOUT5:4 Data, BBOUT6 Sync

See (2)(3)

tskmax (BB)Serial1 BBOUT7 Clk, BBOUT5:4 Data, BBOUT6 Sync

See (2)(3)

310

tskmin(BB)Serial2

BBOUT11 Clk, BBOUT9:8 Data, BBOUT10 Sync

See (2)(3)

tskmin(BB)Serial2

BBOUT11 Clk, BBOUT9:8 Data, BBOUT10 Sync

See (2)(3)

300

tskmax(BB)Nibble0

BBOUT3 Clk, BBOUT5,4,1,0 Data, BBOUT2 Sync

See (2)(3)

170

tskmax(BB)Nibble0

BBOUT3 Clk, BBOUT5,4,1,0 Data, BBOUT2 Sync

See (2)(3)

340

tskmin(BB)Nibble1

BBOUT7 Clk, BBOUT11:8 Data, BBOUT6 Sync

See (2)(3)

tskmax(BB)Nibble1

BBOUT7 Clk, BBOUT11:8 Data, BBOUT6 Sync

See (2)(3)

305

BBOUT7 Clk, BBOUT11:8,5:4,2:0 Data, BBOUT6

tskmin(BB)Byte

See (2)(3)

250

Sync

BBOUT7 Clk, BBOUT11:8,5:4,2:0 Data, BBOUT6

tskmax(BB)Byte

See (2)(3)

255

Sync

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

–40°C.

(2)

Skew measured for RX BBOUT data and frame signals, relative to the BBclk signal at zero crossing. BBclk is measured at threshold

crossing. Lab measurement +signal

→ 50 Ω → Vcommon → 50 Ω → –signal. Vcommon has a 0.01-µF filter capacitor to GND.

Differential probe used for measurement.

(3)

tsu calculation: 1/4 BBclk period – tskmin; th calculation: 1/4 BBclk period – tskmax

Figure 16. RX Baseband LVDS DDR1, DDR2 Output Timing Specifications

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