GC5337 datasheet(41/49 Pages) TI

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TCK

TDI

TDO

T0289-02

T0516-01

SPI Clock

SPIDIO-In

SPIENB

SPIDO(SPARE)

su(DENB)

su(DI)

h(DI)

h(DO)

d(DO1)

GC5330

GC5337

www.ti.com

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

Figure 24. JTAG Timing Specifications

The SPI programming interface is active only when EMIFENA is 0. There are both three-wire and four-wire SPI

interfaces; the SPIDO(SPARE) is the fourth wire for SPI data output.

Table 25. SPI Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tsu(DENB)

Enable setup time before SPI CLK

↑

Valid for SPIDENB, see(1)

tsu(DI)

Data setup time before SPI CLK

↑

Valid for SPIDIO, see(1)

th(DI)

Input data hold time after CLK

↑

Valid for SPIDIO, see(1)

0.6

td(DO)

Output data delay from fTCK↓

Valid for SPIDIO, see(2)

td(DO1)

Output data delay from fTCK↓

Valid for SPIDO(SPARE), see(2)

fclk SPI

SPI clock frequency

See(1)

MHz

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

–40°C.

(2)

The SPI data output in three-wire mode comes from SPIDIO; in four-wire mode the output is from SPIDO(SPARE).

Figure 25. SPI Timing Specifications

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