MPC5606S datasheet(30/136 Pages) FREESCALE

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MPC5606S Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

2.4

Pad configuration during reset phases

All pads have a fixed configuration under reset.

During the power-up phase, all pads are forced to tristate.

After power-up phase, all pads are floating with the following exceptions:

•

PB[5] (FAB) is pull-down. Without external strong pullup the device starts fetching from flash.

•

RESET pad is driven low. This is released only after PHASE2 reset completion.

•

Main oscillator pads (EXTAL, XTAL) are tristate.

•

Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.

•

The following pads are pullup:

—PB[6]

—PH[0]

—PH[1]

—PH[3]

—EVTI

2.5

Voltage supply pins

Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.

There is a preferred power-up sequence for devices in the MPC5606S family. That sequence is described in the following

paragraphs.

Broadly, the supply voltages can be grouped as follows:

•

VREG HV supply (VDDR)

•

Generic IO supply or noise free supply

—VDDA

—VDDE_A

—VDDE_B

—VDDE_C

—VDDE_E

—VDDMA

—VDDMB

—VDDMC

—VDDPLL

•LV supply (VDD12)

The preferred order of ramp up is as follows:

Generic IO supply or noise free supply

VREG HV supply (VDDR - Should be the last HV supply to ramp up. It is also OK if all HV supplies including VDDR

ramp up together)

LV supply

The reason for following this sequence is to ensure that when VREG releases its LVDs, the I/O and other HV segments are

powered properly. This is important because the MPC5606S does not monitor LVDs on I/O HV supplies.

MPC5606S Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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