MPC5606S datasheet(5/136 Pages) FREESCALE

5 / 136 page

MPC5606S Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

Figure 1. MPC5606S series block diagram

1.5

MPC5606S features

1.5.1

Summary

•

Single issue, 32-bit Power Architecture technology compliant CPU core complex (e200z0h)

— Compatible with Power Architecture instruction set

Six Gauge

Drivers

with

Stepper

Stall Detect

(SSD)

16 + 8 ch.

2 ×

DSPI

Test Controller

Nexus 2+

Nexus

SIU

Reset Control

Interrupt

External

IMUX

GPIO &

JTAG

Pad Control

JTAG Port

Nexus Port

e200z0h

External

Blocks

Controller

2 ×

FlexCAN

Peripheral Bridge

Peripheral

Interrupts from

Interrupt

Request

External

Interrupts

I/O

Instructions

Data

Voltage

Regulator

NMI

SWT

STM

NMI

SIU

. . .

(INTC)

4 × I2C

. . .

2 ×

LINFlex

2 x

eMIOS

16 ch.

ADC

Controller

Flash

Power

Control

Mode

Entry

Clock

Generation

Module

Reset

Generation

Module

Unit

Module

BAM

RTC/

SSCM

API

10-bit

. . .

DMA

DCU

RGB TFT

Output

Parallel

Data

(PDI)

Interface

SIRC

FIRC

SXOSC

FXOSC

XTAL/

EXTAL

XTAL32/

EXTAL32

16 MHz

128 kHz

4–16 MHz

32 KHz

4 × PIT

LCD FP

and

BP signals

Sound

Generation

speaker/

buzzer

Data

and

Clock

QuadSPI

Controller

SRAM

2 ×

FMPLL

Port

Controller

Video

Controller

SRAM

40 × 4

LCD

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