MPC5606S datasheet(61/136 Pages) FREESCALE

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MPC5606S Microcontroller Data Sheet, Rev. 6

Freescale Semiconductor

3.4.2

Connecting power supply pins: What to do and what not to do

•Do:

— Have all power/ground supplies connected on the board from a strong supply source rather than weak voltage

divider sources unless there is “NO IO activity” in the section

— Meet the supply specifications for max / typical operating conditions to guarantee correct operation

— Place the decoupling near the supply/ground pin pair for EMI emissions reduction

— Route high-noise supply/ground away from sensitive signals (for example, ADC channels must be away from

SMD supply/motor pads)

— Use star routing for the ballast supply from the VDDR supply to avoid ballast startup noise injected to VDDR

supply of the device

— Use LC inductive filtering for ADC, OSC, and PLL supplies if these are generated from common board regulators

VDDE_B SR C Voltage on VDDE_B (I/O supply) pin with

respect to ground (VSSE_B)

—4.5

5.5

VDDE_C

7 SR C Voltage on VDDE_C (I/O supply) pin with

respect to ground (VSSE_C)

—4.5

5.5

VDDE_E SR C Voltage on VDDE_E (I/O supply) pin with

respect to ground (VSSE_E)

—4.5

5.5

VDDMA SR C Voltage on VDDMA (stepper motor supply)

pin with respect to ground (VSSMA)

—4.5

5.5

VDDMB SR C Voltage on VDDMB (stepper motor supply)

pin with respect to ground (VSSMB)

—4.5

5.5

VDDMC SR C Voltage on VDDMC (stepper motor supply)

pin with respect to ground (VSSMC)

—4.5

5.5

VSSOSC SR C Voltage on VSSOSC (oscillator ground) pin

with respect to VSS

—0

VLCD

SR C Voltage on VLCD (LCD supply) pin with

respect to VSS

—0

VDDE_A +0.3

TVDD

SR C VDD slope to ensure correct power up

—

10–6

0.25

V/µs

SR C Ambient temperature under bias

—

40

105

°C

SR C Junction temperature under bias

—

40

150

°C

1 100 nF capacitance needs to be provided between V

DDA/VSSA pair.

2 Full functionality cannot be guaranteed when voltage drops below 4.5 V. In particular, I/O DC and ADC electrical

characteristics may not be guaranteed below 4.5 V during the voltage drop sequence.

3 10 µF capacitance must be connected between V

DDR and VSS12. This is required because of sharp surge due to

external ballast.

4 V

DD refers collectively to I/O voltage supplies, i.e., VDDE_A, VDDE_B, VDDE_C, VDDE_E, VDDMA, VDDMB and VDDMC.

5 100 nF capacitance needs to be provided between each V

DD/VSS pair

6 V

SS refers collectively to I/O voltage supply grounds, i.e., VSSE_A, VSSE_B, VSSE_C, VSSE_E, VSSMA, VSSMB and

VSSMC) unless otherwise noted.

7 V

DDE_C should be the same as VDDA with a 100 mV variation, i.e., VDDE_C = VDDA 100 mV.

Table 16. Recommended operating conditions (5.0 V) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

MPC5606S Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc

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