SL811HS

Document 38-08008 Rev. *F

Page 18 of 32

USB Address Register, Address [07h]

This register contains the USB Device Address after assignment by USB host during configuration. On power-up or reset, USB

Address register is set to Address 00h. After USB configuration and address assignment, the device recognizes only USB transactions

directed to the address contained in the USB Address register.

Interrupt Status Register, Address [0Dh]

This read/write register serves as an Interrupt Status register when it is read, and an Interrupt Clear register when it is written. To clear

an interrupt, write the register with the appropriate bit set to ‘1’. Writing a ‘0’ has no effect on the status.

Current Data Set Register, Address [0Eh]. This register indicates current selected data set for each endpoint.

Control Register 2, Address [0Fh]. Control Register 2 is used to control if the device is configured as a master or a slave. It can

change the polarity of the Data+ and Data- pins to accommodate both full- and low speed operation.

Table 30. USB Address Register [Address 07h]

7

6

5

4

3

2

1

0

USBADD7

USBADD6

USBADD5

USBADD4

USBADD3

USBADD2

USBADD1

USBADD0

Table 31. Interrupt Status Register [Address 0Dh]

7

6

5

4

3

2

1

0

DMA Status

USB Reset

SOF Received

DMA Done

Endpoint 3

Done

Endpoint 2

Done

Endpoint 1

Done

Endpoint 0

Done

Bit Position

Bit Name

Function

7

DMA Status

When equal to ‘1’, indicates DMA transfer is in progress. When equal to 0, indicates DMA

transfer is complete. An interrupt is not generated when DMA is complete.

6

USB Reset

USB Reset Received Interrupt.

5

SOF Received

SOF Received Interrupt.

4

DMA Done

DMA Done Interrupt.

3

Endpoint 3 Done

Endpoint 3 Done Interrupt.

2

Endpoint 2 Done

Endpoint 2 Done Interrupt.

1

Endpoint 1 Done

Endpoint 1 Done Interrupt.

0

Endpoint 0 Done

Endpoint 0 Done Interrupt.

Table 32. Current Data Set Register [Address 0Eh]

7

6

5

4

3

2

1

0

Reserved

Endpoint 3

Endpoint 2

Endpoint 1

Endpoint 0

Bit Position

Bit Name

Function

7-4

Reserved

Not applicable.

3

Endpoint 3 Done

Endpoint 3a = 0, Endpoint 3b = 1.

2

Endpoint 2 Done

Endpoint 2a = 0, Endpoint 2b = 1.

1

Endpoint 1 Done

Endpoint 1a = 0, Endpoint 1b = 1.

0

Endpoint 0 Done

Endpoint 0a = 0, Endpoint 0b = 1.

Table 33. Control Register 2 [Address 0Fh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SL811HS

Master/Slave

selection

SL811HS

D+/D– Data

Polarity Swap

Reserved

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