SL811HS datasheet(19/32 Pages) CYPRESS

19 / 32 page

SL811HS

Document 38-08008 Rev. *F

Page 19 of 32

SOF Low Register, Address [15h]. Read only register

contains the 7 low order bits of Frame Number in positions: bit

7:1. Bit 0 is undefined. Register is updated when a SOF packet

is received. Do not write to this register.

SOF High Register, Address [16h]. Read only register

contains the 4 low order bits of Frame Number in positions: bit

7:4. Bits 3:0 are undefined and should be masked when read by

the user. This register is updated when a SOF packet is received.

The user should not write to this register.

DMA Total Count Low Register, Address [35h]. The DMA

Total Count Low register contains the low order 8 bits of DMA

count. DMA total count is the total number of bytes to be trans-

ferred between a peripheral to the SL811HS. The count may

sometimes require up to 16 bits, therefore the count is repre-

sented in two registers: Total Count Low and Total Count High.

EP3 is only supported with DMA operation.

DMA Total Count High Register, Address [36h]. The DMA

Total Count High register contains the high order 8 bits of DMA

count. When written, this register enables DMA if the DMA

Enable bit is set in Control Register 1. The user should always

write Low Count register first, followed by a write to High Count

Bit Position

Bit Name

Function

7SL811HS

Master/Slave

selection

Master = ‘1’

Slave = ‘0’

SL811HS D+/D–

Data Polarity Swap

’1’ = change polarity (low speed)

’0’ = no change of polarity (full speed)

5-0

Reserved

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