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SL811HS Datasheet(PDF) 28 Page - Cypress Semiconductor |
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SL811HS Datasheet(HTML) 28 Page - Cypress Semiconductor |
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28 / 32 page  SL811HS Document 38-08008 Rev. *F Page 28 of 32 DMA Read Cycle Note Data is held until nDACK goes high regardless of state of nREAD. Reset Timing Note Clock is 48 MHz nominal. Parameter Description Min Typ Max tdack nDACK low 100 ns tddrdlo nDACK to nRD low delay 0 ns tdckdr nDACK low to nDRQ high delay 5 ns tdrdp nRD pulse width 90 ns tdhld Date hold after nDACK high 5 ns tddaccs Data access from nDACK low 85 ns tdrdack nRD high to nDACK high 0 ns tdakrq nDRQ low after nDACK high 5 ns trdcycle DMA Read Cycle Time 150 ns n DRQ n DAC K D0-D 7 DA T A n RD S L 811 D M A R E A D C Y C L E T IM IN G tdrdp tdaccs tdack tdhld tddrdlo tdckdr tdakrq SL811 DMA Read Cycle Timing nRST treset nRD or nWR tioact Reset Timing Parameter Description Min Typ Max tRESET nRst Pulse width 16 clocks tIOACT nRst HIGH to nRD or nWR active 16 clocks [+] Feedback |
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